Homework Assignment #5
EE 477 Spring 2011 Professor Parker
Hardcopies due 8:30 AM 4/18/2011 1st Floor of EEB, west side of building
Ecopies due 11:59 PM 4/17/2011 using the "Assignment" Function on DEN
Solutions will be posted 10 AM 4/18/2011
This assignment is worth 1.5 regular homework assignments
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.
Use these parameters for the calculation:
βn = 340.4 μA/V2, βp = -70.8 μA/V2
Vdd= 1.8 V, Vtp = - 0.4 V, Vtn = 0.4 V, Vtp,BE = - 0.5 V, and Vtn,BE = 0.5 V.
Tox = 41 angstroms for thinox, and 5000 angstroms for thick oxide.
ε0 (epsilon) = 8.85 X 10 -14 F/cm and εoxide(epsilon) = 3.9.
lambda = 0.1 micron.
Cjbsn = 9.725 x 10-4 pF/ μm2 and Cjbswn = 2.27 x 10-4 pF/ μm (micrometer). Assume drain is the same.
Cjbsp = 11.57 x 10-4 pF/ μm2 and Cjbswp = 1.8 x 10-4 pF/ μm (micrometer). Assume drain is the same.
xj (diffusion depth) = 0.1 microns.
Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide.
1. (a) (10%) Size the transistors in a 4-input NOR gate so that the worst-case rise times are twice the length of the fall times, assuming the smallest transistors are unit size.
(b) (5%) Show an equivalent circuit of the NOR gate, with all capacitances shown. For the equivalent circuit, you can assume worst case rise time. Label the inputs and explain the combination of input changes that gives worst case rise time.
2. (15%) Use the Fringing Field Capacitance graph shown on p.247 of the text. Compute the total capacitance of a metal1 wire by first computing the parallel plate capacitance then using the graph to compute total capacitance. Assume the metal thickness is 1 μm. The metal is 5 lambda wide, and 12.5 lamda long. Assume the metal is over the substrate with no other layers in between except the SiO2 insulation.
3. For the compound gate circuit shown in the Spring 2007 Homework 5 solution to Problem 4 ( a better image of the same compound gate is found in the Spring 2007 solution to Homework 2 p. 3) assume we do not know the arrival time of the inputs. Assume the smallest PMOS/NMOS transistors are unit-size with effective channel resistance Rp and Rn and diffusion capacitance Cdp and Cdn.
(a) (5%) First, assume all unit-size transistors. Identify a critical path on the PMOS side that gives worst-case rise time, and on the NMOS side that gives worst-case fall time. Specify the input transitions that give the worst case timing.
(b) (10%) Size the transistors in this compound gate so that the worst-case rise time = worst-case fall time.
(d) (10%) How many diffusion capacitances get charged/discharged in the worst case, assuming no diffusion regions are shared?
(e) (10%) Compute the worst-case falling RC time constant at the output using a lumped model, in terms of the variables given above.
(f) (10%) Compute the worst-case falling RC time constant at the output using an Elmore delay model, in terms of the variables given above.
4. (10%) Compute the gate capacitance of an NMOS transistor that has dimensions 2.5 Ũ minimum width, and 2.1 Ũ minimum length. How does Cg change if the transistor is scaled so that s=3?
5. (15%) Compute the diffusion capacitance of the drain of the NMOS transistor in Problem (4), assuming minimum diffusion length. Use the method described in the lecture and the text. Note that this method might differ from past homework solutions.
6. (15%) Ernie Engineer designed an inverter driving a long wire (6 mm) on a special kind of metal1 (3 lambda wide) to the input of another inverter. Both the inverters have identical unit-size transistors. Ernie's boss wants Ernie to insert a pair of inverters each of which in the one-third of the wire, so the long wire is divided into three wires. Do you think Ernie will improve his wire delay if he inserts this pair of inverters? Explain your answer. Use the following parameters in this problem.
The capacitance of this special kind of metal is 10 ff per millimeter. The resistance is 0.01 ohm per square.
Cgn=Cgp = 100 ff, Rchn = 500 ohms, Rchp = 1000 ohms, Cdn = Cdp = 40 ff for unit size transistors.
7. (10%) Compare the lumped and distributed delays of a wire 2000 μm long and .5 μm wide , with resistance .08 ohms per □ square, and capacitance .01 ff/μm.
8. (10%) An NMOS transistor has gate capacitance Cg= 17 ff when Vgs = 2.5 V and Vgs = 0.0 V. Approximate the gate capacitance when the transistor is in saturation.
9. (10%) How would the fall time in the saturation region change if I used an equation for drain current Ids = (βn/2)(Vgs - Vtn)?
10. (10%) Assume the network of gates shown in Lecture 18, p. 4, using the same assumptions about capacitance and channel resistance used in class. Compute the rise time between gates 3 and 4. Add an extra input p to gate 3, and recompute the rise time between gates 3 and 4.