Homework Assignment #3

EE 477 Spring 2011 Professor Parker

Hardcopies due 5 PM 2/15/2011 1st Floor of EEB, west side of building

Ecopies due 11:59 PM 2/15/2011 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

1. (15%) Use the compound gate shown below Label the sources and drains of all transistors. Show an identical Euler path for both NMOS and PMOS transistors by listing transistor inputs on both paths. The inverter at the end of the compound gate does not have to be in the Euler path.

2. (20%) Give a stick diagram for the compound gate in Problem 1 above, using the Euler path you found.

3. (15%) A design has a number of common inputs/outputs that need to be connected. Use the left edge algorithm to connect common inputs using as few tracks as possible. The starting and ending positions of each common input are given below. You can assume the inputs come from either the top or the bottom of the channel to make the problem easier.

A (3,10)

B (8,13)

C (1,7)

D (11,14)

E (5,9)

F( 9,12)

G (1,4)

4. (25%) Use Cadence to draw a complete schematic of your design of the compound gate from problem 1. Capture/print your schematic.

You can use the inverter symbol you created in lab. Transistors are unit-sized. Be sure the symbols of vdd and gnd are present in your schematic even though they may not be "visually connected" to anything.

Notes: In the schematic, if wires(nets) share the same name, they are considered connected together even though they may not be "visually wired." If wires/nets are given the same name as a pin name, they are considered connected to that pin. Apply this technique to make your schematic design more readable.

To name a wire/net, select Create->Wire Name or press "L" (hot key for adding wire name). An 'Add Wire Name' window will open up. Put the wire name in the Names field and leave everything else as defaults. Then back to the Schematic Editor window, double click on the wire. Close the 'Add Wire Name' window after you have done adding all wire names.

Instructions to print schematic in black and white: (It is preferred that you submit printed schematics, but it is optional in this assignment.)

In the Schematic Editor, select File->Print. A 'Submit Plot' window will open up. Click on Plot Options in the lower right corner. Set Plotter Name to 'Generic 300 dpi Adobe Post Script Level 1 Plotter' (for B/W images.) Check the box Send Plot Only To File and give a file name in the form myfilename.ps. Click 'OK' to save the Plot Options and 'OK' to Submit Plot.

5. (25%) Sketch an inverter layout by hand showing dimensions of the following features: transistor sizes, poly gate extension, and n-diffusion contact. Show each layer in color. Use the minimum size dimensions where possible, except make the PMOS transistor 3 times unit width and twice unit length, and the NMOS transistor unit width and twice unit length. Assume the input comes in on poly and the output is on metal 1. Be sure to show Vdd and Gnd.

You may also use Cadence Virtuoso to draw the layout.

Instructions to print layout in color:

In the Layout Editor, select File->Export Images. Save the image in PNG format. Type myfile.png in the Filename field. You can set the Background as 'Transparent' for white background or as 'Solid' for black background.

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