Homework Assignment #2

EE 477 Spring 2011 Professor Parker

Hardcopies due 5 PM 2/8/2011 1st Floor of EEB, west side of building

Ecopies due 11:59 PM 2/8/2011 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

1. (35%) Design a circuit that recognizes a sequence of 3-bit inputs. The sequence is 001 001 010 101. The output goes high after all 4 inputs are received in order. Each flip flop should contain two latches, as described in class. The data loaded into the flip flop will depend on the data currently in the flip flop along with data in the other flip flops and the inputs.

Your flip flops should be designed at the gate level. Use NAND gates to build the multiplexer at the input to each latch.

Show your solution for the entire circuit as a gate-level diagram.

2. (15%) Draw a transistor (circuit) level diagram for a compound gate that implements the following Boolean function

G = (W + X + Y)(Z + /W)(V + /Y)

You can assume that V, W, X, Y and Z as well as their complementary inputs are available. Label the sources and drains of all the transistors.

3. (10%) Sketch the side view (slice down into the silicon) of a staggered contact that connects n+ diffusion to metal3 using colored pens or pencils.

4. (5%) List the steps needed to pattern metal4 using a positive photoresist process.

5. (5%) Connecting the NWell to Vdd reverse biases which diodes in an NWell process?

6. (15%) In the attached figure below, show the cross-section down into the silicon along the vertical white line.

7. (5%) What can happen when MOS parasitic transistors form?

8. (10 %) What major problem could occur when poly does not have a gate extension in a conventional CMOS process?