EE477 - s10 lab3

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 (worth 20% of final grade)

Module Design, Cadence and SPECTRE

Due 5/7/10 11:59 PM

There will be no extensions so plan your time accordingly!

This lab addresses the design of a special-purpose circuit. The circuit is a network of simplified digital neurons. There are two parts to the lab, the design of the digital neuron (worth 10%) and the design of the neural network (worth 10%).

1. The digital neuron

There are many inputs to the neuron:

5 data inputs to the neuron, A, B, C, D and E, that could be different every clock cycle
a single-bit inhibitory input I,
Load control signal, that allows the output ff to be loaded with a new value,
and a clock with 50% duty cycle.

Name your signals as shown in bold above. The output should be named AP. It is important you follow this naming convention so we can verify that your circuit works.

The basic Neuron Function:

Each data input and control input has a single bit.
The inhibitory input I is a single bit.
You need to generate all inverted inputs, including /clock.
The neuron output contains a firing flip-flop, and the output of the flip-flop AP represents the output of the neuron.
When each data input A, B, C, D or E is high, If the total number of high inputs equals or exceeds 3, the neuron "fires," as long as I is held high. If the number of high inputs is 5, the neuron "fires" no matter what I is. The conditions for firing are recomputed when new inputs A, B, C, D, E and I are loaded.
The inhibitory input I is basically a veto that prevents the neuron from "firing" when it is asserted low and all 5 other inputs are not high.
After the positive edge of the clock, if the neuron fires, the output of the firing flip-flop goes from low to high. After the next rising clock, the firing flip-flop output falls unless it is firing again.
Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance.
Note that the computation the neuron contains is not exactly the same as the compound gate you designed, but you might find a way to use the compound gate.

A block diagram of the neuron is shown below.

Neuron input/output list:

A - 1 bit
B - 1 bit
C - 1 bit
D - 1 bit
E - 1 bit
I - 1 bit
Load - 1 bit
Clock - 1 bit
AP (output ff) - 1 bit

Rules:

You can use any combination of multiple clocks you wish, but only clock is an input to the circuit and you will have to design circuits to generate the other clocks.
/load is not an input to the circuit. You need to generate it if you need it.
You must use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells unless your cells do not meet the requirements of lab 1 (i.e. you lost points).
You must have ntaps and ptaps according to the rules.
You cannot remove unused logic from your cells.

The Neuron Laboratory Goal

You will produce a working schematic and layout for the neuron.

Layout Instructions for The Neuron:

1. Make sure your ohmic contacts meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course they should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts, as Cadence will do for you automatically.

2. You can use metal layers 1-3 for the neuron.

3. For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product of the entire neural network. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.

4. Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected.

The Laboratory Steps:

1. Design your neuron circuit and create a Cadence circuit (schematic) diagram using the circuits/cells you have already designed in Labs 1 and 2. You cannot design new cells for

Lab 3. Include your logic/gate level diagram for your neuron.

2. Simulate your neuron schematic with SPECTRE to ensure that your design works correctly.

Use the following sequence of inputs for initial testing:

a) Set load to 1and keep it high. All other inputs should be 0. Clock the circuit. You are resetting your neuron flip flop by loading in zero.

b) Then test your neuron by sequencing through all combinations of inputs starting with ABCDE = 00000, then 00001, then 00010 until you reach 11111, while holding I high (no inhibition) and clocking the circuit. The output should be high when at least three of the inputs are high.

c) Now set I = 0 (inhibition) and sequence through these inputs: ABCDE = 00001, 00011, 00111, and 11111. The output AP should be low until after the inputs 11111.

d) Reset the neuron flip flop with zero. Now set load to 0 (zero). Set ABCDE = 11111, and I = 1. The flipflop output should remain zero.

3. Design and simulate your neuron layout with SPECTRE using the same sequence of inputs as in Step 2. You can modify the layout of your cells from Labs 1 and 2 in minor ways in Lab 3 if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Testing Strategy for Part 1

Here is a testing strategy that might be useful to you: Design the schematic first and test. Then design the layout.

Design and test at each stage. Design the output flip-flop first. Then design the logic and the output of the logic that makes the neuron fire if the logic creates a "fire" situation. Test the logic separately first. Then add the flip-flops. Then test the entire neuron

2. The "line detection" neural network

This part of the lab addresses the design of a special-purpose circuit to detect a line that passes through the center of an image that is 5X5 pixels in size. Lines appear as 1's in the image, and otherwise pixels are 0's. The basic building block in the circuit is a very simplified digital neuron that you built in Lab 3 Part 1. You will build a small network with this neuron and inverter as basic building blocks in this part of Lab 3. You can use all 6 metal layers for the network.

For the project, you are to assemble a "neural net" using 14 of these neurons. We will tell you all the inputs, conditions, and outputs.

Operation of the Neural Network:

The first four neurons detect specific lines in an input image that is 5X5 pixels. Pixel P31 is the pixel in the 3rd column and first row. Neuron V detects a vertical line through the middle of the image and has as inputs P31, P32, P33, P34 and P35. Neuron H detects a horizontal line through the middle of the image and has as inputs P13, P23, P33, P43, P53. Neuron DR has as inputs pixels P15, P24, P33, P42, P51. Neuron DL has as inputs P11, P22, P33, P44, and P55. All these neurons have their inhibitory inputs tied to Vdd.

Six neurons detect the outputs of the first stage neurons. Four of the neurons just relay the outputs of the first four neurons to the final stage of neurons. They have two other inputs tied to Vdd and two to ground. The inhibitory inputs are tied to Vdd. Two of the neurons detect error conditions when both horizontal and vertical lines are present, or cross diagonals are both present. These have one input tied to Vdd, two to gnd, and inhibitory inputs are primary inputs. The output stage neurons have as inputs one relay neuron each, two inputs tied to Vdd, two to gnd, and an inhibitory input tied to an inverted output of an error neuron.

The neurons in the final stage reveal final lines detected as long as there are no error conditions.

You cannot remove logic or inputs from the neurons. If they are unused you have to tie inputs to Vdd or Gnd as shown in the figure.

There are 17 pixel inputs and the other pixels are ignored. There are two inhibitory inputs to the two error neurons. There are four outputs Vfinal, Hfinal, DRfinal and DLfinal, and control inputs load, and clock. You can't test all combinations of the inputs. Load should be kept high for all cycles unless told otherwise. Clock cycle 1 is the period when the clock is low followed by the clock high.

Reset all neurons by loading zeros into all four input neurons and clocking repeatedly until all neuron flip-flops contain 0's. .

In clock cycle 1, load zeros into all four input neurons. Set the load, ErrorV/H and ErrorD inputs to high. Keep load high. At the end of the high clock, all neuron outputs should be low.

In clock cycle 2, set all P's to 1. Set the ErrorV/H and ErrorD inputs to high. At the end of the high clock, all neuron outputs should be low except neurons 1-4 should be high.

In clock cycle 3, set all P's to 1. Set the ErrorV/H and ErrorD inputs to low. At the end of the high clock, all neuron outputs should be high except neurons 9-14 should be low.

In clock cycle 4, set all P's to 1. Set the ErrorV/H and ErrorD inputs to high and hold them there until told to lower them. At the end of the high clock, all the neuron outputs should be high because you have inhibited the error signals in the previous cycle.

In clock cycle 5 set all P's to 0 except P31, P32, P33, P34 and P35. At the end of the high clock, the outputs 2-4 and 11-14 should be zero and the rest 1.

In clock cycle 6, set all P's to 0 except P13, P23, P33, P43, P53. At the end of the high clock,, the outputs 1, 3-4, and 6-14 should be zero and the rest 1.

In clock cycle 7, set all P's to 0 except P15, P24, P33, P42, and P51. At the end of the high clock,, the outputs 1, 2, and 4, 5, 7-10 and 12-14 should be zero and the rest 1.

In clock cycle 8, set all P's to 0 except P11, P22, P33, P44, and P55. At the end of the high clock,, the outputs 1-3, 5-6, 8-11 and 13-14 should be zero and the rest 1.

In clock cycle 9, set all P's to 0 except P15, P24, P33, P42, P51, P11, P22, P44, and P55. At the end of the high clock, the outputs 1-2, 5-7, 9-12 and 14 should be zero and the rest 1.

In clock cycle 10, set all P's to 0 except P15, P24, P33, P42, P51, P11, P22, P33, P44, and P55 . At the end of the high clock, the outputs 1-2, 5-6, 9, and 11-13 should be zero and the rest 1.

In clock cycle 11, set all P's to 0 except P15, P24, P33. set ErrorV/H and ErrorD low. At the end of the high clock, the outputs 3, 7, and 8 will be high.

In clock cycle 12, set all P's to 0 except P13, P23, P33, P43, P53, and P31. Set the ErrorV/H and ErrorD inputs to high and hold them there. The outputs should be zero except for neuron 2, 7, 13 and 14. AP=DLfinal and AP-DRfinal should both be high, since we inhibited the error signal checking in the previous clock cycle.

In clock cycle 13, set ErrorV/H and ErrorD low, and set all P inputs high. Neurons 1-4 and 6 should be high at the end of the high clock. AP-DRfinal, neuron 13, should be high.

In clock cycle 14, hold all inputs high except ErrorV/H and ErrorD. all neuron outputs should be high except neurons 9, 10, 11, 13 and 14. AP-Hfinal should be high.

In clock cycle 15, hold all inputs high. All neuron outputs should be high.

This timing diagram should clarify the test sequence above. IMPORTANT: I am showing the outputs of the neurons changing state (rising or falling) at the end of the clock cycle that caused the change. The outputs might fall more quickly than I have shown.

Design Requirements:

You can use any combination of multiple clocks you wish, but only clock is a clock input to the circuit and you will have to design circuits to generate the other clocks. /load is not an input to the circuit. You need to generate it if you need it.

You should use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells or the transistor sizes unless the rise/fall times do not meet the requirements of lab 1. However, you can modify the layout in minor ways if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Make sure your ohmic contacts meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course they should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact.

You can use metal layers 1, 2 and 3 for the neuron. You can use metal layers 1-5 for the entire neural network.

The diagram below shows how the neurons are to be connected.

The Neural Network Laboratory Design Goal

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.

The Laboratory Steps For the Neural Network

1. Design your circuit and create a Cadence circuit (schematic) diagram and a Cadence layout using the cells you have already designed. You cannot design new cells for Lab 3. You can continue to make minor adjustments to the layouts and tune transistor sizes if you like. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram for your neuron. Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected. Route all inputs and outputs to the edges of the layout.

2. Simulate your schematic and layout with SPECTRE to ensure that your design works correctly The inputs, intermediate outputs and final output to your project circuit should be named exactly as we have named them here. It is important you follow this naming convention so we can verify that your circuit works. You will not be able to simulate all possible inputs. Choose your cases wisely if you decide to simulate more cases than those required. Please simulate the timing diagram given in the lab assignment with inputs in the exact order we specify.

3. The delay you should measure with SPECTRE is the clock cycle. The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock cycle. If you compute the area-delay product wrong, or you do not compute it you will lose points.

4. Upload your report to the assignments function of Blackboard, including your layout and simulation files as a TAR file just like you did in lab 2 so that we can test (simulate) your circuit to be sure it performs as specified. Be sure to include your SPECTRE input files for the project.

Lab Report Contents:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number.
A description of the neuron you built, including a transistor-level or gate-level circuit diagram printed from Cadence.
A floorplan of the neuron layout.
Your neuron layout and neuron layout simulation results. Make sure the layout and simulation images are of high enough resolution so that we can zoom in to check things.
A description of the network you built, including a gate or transistor level circuit diagram printed from Cadence.
The neural network layout screen capture, in a high resolution so we can zoom in.
A description of the simulation experiments you ran with SPICE for the network.
SPECTRE netlist files generated by Cadence, which will include the technology file, the input stimulus file and the circuitry netlist.
SPECTRE outputs for the neural network schematic and layout.

Items 1-7 should all be in a single report. Tar this report along with the files specified in items 8 and 9, and upload to the assignments page of the blackboard.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.