Homework Assignment #6

Spring 2010 EE 477

Due April 20, 2010 11:59 PM, online

Solutions will be posted morning of April 21

Assume lambda is .125 microns. Assume Vdd is 2.5v. Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is 0.50 microns. You can use these values for transistor betas: βn (beta)= 219.4 W/L μ A(microamps)/V² and βp (beta)= 51 W/L μ A/V² . R_s = 4 ohms for poly.

1(10 %). A 2-input NOR gate drives an inverter through a long wire and a transmission gate is placed 1/4 of the way along the wire. C_Dn = C_Dp = 5 ff for each source and drain, and C_gn = C_gp = 20 ff, R_chn = 1000 ohms and R_chp = 4300 ohms, and the wire has resistance R_int = 100 ohms and capacitance C_int = 8 ff. Compare the rise and fall times at the input to the inverter using lumped time constants.

2 (8 %). An NMOS transistor has gate capacitance C_g= 17 ff when V_gs = 2.5 V and the transistor is in saturation. Approximate the gate capacitance when V_gs = 0.0 V.

3 (7 %). Ernie Engineer uses metal1 to connect two cells in his circuit. The metal is 3 lambda wide and 190 lamdba long. The metal resistance R= 0.6 ohms. What is the sheet resistance R_s of the metal?

4 (10 %). Connect an output of an inverter to the input of a second inverter. For the inverters, assume Rchn=1000 ohms and Rchp = 4000 ohms, Cgn=Ggp=Cdn=Cdp=10 ff. Compare the fall time constant at the output of the driving (first) inverter to the fall time constant at the output of the first inverter with the width of the transistors in the driving inverter multiplied by 4.

5 (10 %). Assume a metal1 interconnect 40 lambda long is subject to fringing fields. Use the curves shown in Fig. 6.18 (Kang and Leblebici) to approximate the fringing field factor for the modified output metal interconnect 8 lambda wide. Reading C/Cpp off the figure is not easy so just approximate, noting that the y axis is a log scale. Points will not be deducted for inexact answers.

6. (5 %) What happens to power consumption per transistor with constant E-field scaling?

7. (10 %) For the network of gates shown on page 18-9 of Lecture 18, compute the total longest delay through the network starting with the rise time at the output of gates 1 and 5. Assume C_d = 2C_g.

8. (10 %) A wire stretches 2.6cm across a CMOS chip. Assuming the rise and fall times are 1.2ms on the wire, and the velocity of the electrons is 0.00028 meters per second. Should we consider inductance in our wiring parasitics?

9. (15%) Rework problem 1 using Elmore delay to find the rising and falling time constants at the output of the NOR gate. Find the time constants at the output to the transmission gate as well.

10. (15%) Assume the wire in Problem 8 has resistance .00055 ohms/micron, and capacitance .0033 ff/micron. Compute the wire delay using the lumped wire delay model and the distributed wire delay model and compare them.