Homework Assignment #5

Prof. Parker Due April 14, 5 PM in EEB or electronic submissions due at 11:59 PM EE 477 Spring 2010

Assume V_dd = 2.5 v. for these problems. Assume V_tp is -.7 V. Assume V_tn is .7 V. T_ox = 57 angstroms for thinox, and 5000 angstroms for thick oxide.

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9.

lambda = .120 microns.

C_jbsn = 17.27 x 10^-4 pF/ μm² and Cjbswn = 4.17 x 10^-4 pF/ μm (micrometer). C_jbsp = 18.8 x 10^-4 pF/ μm2and C_jbswp = 3.17 x 10^-4 pF/ μm (micrometer).

x_j (diffusion depth) = 0.1 microns.

1. a) (10%) Size the transistors in a 6-input NAND gate so that the worst-case rise times are 1.2 times the length of the fall times, assuming the smallest transistors are unit size.

b) (5%) Show an equivalent circuit of the NAND gate, with all capacitances shown. For the equivalent circuit, you can assume worst case rise time. Take into account sequences of inputs when considering worst case.

2. (10%) Size the transistors in a 7-input NOR gate so that the worst case rise and fall times are equal, assuming the smallest transistors are 1.5 time unit width and are unit length. Label the inputs and explain the combination of input changes that gives worst case rise and fall times.

3. (10%) An inverter outputs a signal that is added to noise. The inverter only outputs the values Vdd and Gnd, and nothing in between in steady state. If the noise has peak-to-peak amplitude of 0.5v, what should V_ILMAX and V_IHMIN be in order for there to be nonzero noise margins?

4 a) (10%) For the compound gate shown in the solution to Assignment 1 problem 4, identify a critical path on the PMOS side that gives worst-case rise time, and on the NMOS side that gives worst case fall time, ignoring the output inverter. Specify the combination of previous inputs and present inputs that gives worst-case rise time.

b) (10%) Size the transistors in problem 4 of Assignment 1 on the critical path so that rise time = fall time.

c) (10%) Size the NMOS transistors X_i+2 and /y_i+2 on the far left so the resistance in the path containing those transistors equals the resistance in the NMOS critical path.

d) (5%) How many diffusion capacitances charge/discharge in the worst case, assuming no diffusion regions are shared?

e) (5%) Compute the worst case falling RC lumped time constant for this compound gate , in terms of R_chn for a unit size transistor, C_dp and C_dn, and C_gp and C_gn.

5. (15%) Compute the gate capacitance of an NMOS transistor that has dimensions 4.9 × lambda, and 4.5 × lambda. How does Cg change if the transistor is scaled so that s=3?

6. (15%) Compute the diffusion capacitance of the drain of a PMOS transistor that has dimensions 6 lambda wide by 7.5 lambda long (diffusion width is the same as the channel width). Use the method described in the lecture and the text. Note that this method might differ from past homework solutions.

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