A. Parker EE 477L Spring 2010

Homework Assignment #3Due in EEB 2/23/10 5 PM or on line 11:59 PM

1. (15 %) Use the compound gate shown here. Label the sources and drains of all transistors. Show an identical Euler path for both NMOS and PMOS transistors by listing transistor inputs on both paths.

2. (20 %) Give a stick diagram for the compound gate in Problem 1 above, using the Euler paths you found.

3. (15 %) A design has a number of common inputs/outputs that need to be connected. Use the left edge algorithm to connect common inputs using as few tracks as possible. The starting and ending positions of each common input are given below. You can assume the inputs come from either the top or the bottom of the channel to make the problem easier.

A (8,15)

B (9,12)

C (13,16)

D (1,8)

E (1,7)

F( 2,8)

G (9,11)

4. (25 %) Use Cadence schematic capture to draw a schematic of your design from Problem 1. You can use unit-size transistors. Capture your schematic. If you want the black background you can use a "print screen" (PC) or "Grab" (MAC) command. If you want black circuit on white background (better for printed schematics) use the following procedure: Open your schematic. Pull down the design menu and click on plot, then on submit. A submit plot window will open up. Click on plot options in the lower right corner and select send plot only to file and give a file name. The filename should be of the form myfilename.ps. Then type distill myfilename.ps to get a pdf file.

5. (25 %) Sketch an inverter layout showing dimensions of each feature. Use colored pens or pencils. Use the minimum size dimensions where possible, except make the PMOS transistor six times minimum width. Make the NMOS transistor twice minimum width. You can use graph paper or a grid background to show dimensions. Assume the input comes in on poly and the output is on metal 1. Be sure to show Vdd and Gnd, and the well and substrate contacts. Show the nwell.