Homework Assignment #2

EE 477 Spring 2010 Professor Parker

Due 2/11/10 in the box in EEB or via the assignment function on DEN at 11:59 PM

1. (25%) Counters are often used in digital designs when "increment by 1" and "decrement by 1" functions are desired.

Design a binary counter that counts down continuously from 5 to 0 when the clock rises and then resets to 5 when it reaches 0 or when reset is asserted. Reset is a synchronous signal. The counter is reset when the clock rises.

Each bit of storage should be a positive edge-triggered flip flop. Each flip flop should contain two latches, as described in class. Each flip flop should load new data when clock rises IF the reset signal is not asserted. The data loaded into the flip flop will depend on the data currently in the flip flop along with data in the other flip flops

Your counter should be designed at the gate level except for the multiplexers. Use NAND gates to build the multiplexer at the input to each latch. Remember that new data is only stored if reset is not asserted. You might find it helpful to write the logic function for the multiplexer before producing the design.

Show your solution for the counter as a gate-level diagram.

2. (10%) Assume you have 2-to-1 muxes built using transmission gates. Assemble them to construct the logic function that performs a full adder sum S = ABC + A(/B)(/C) + (/A)(/B)C + (/A)B(/C) / means "NOT".

3. (20%) Draw a transistor (circuit) level diagram for a compound gate that implements the following Boolean function

/graduation=/{[(27graduatecredits+8transfercredits*19additionalcredits)*3.0GPA*billspaid]+[131units*2.0GPA*billspaid] }

Label the sources and drains of all the transistors.

4. (10%) Sketch the side view (slice down into the silicon) of a stacked contact that connects metal2 to metal4 using colored pens or pencils.

5. (5%) List the steps involved in patterning polysilicon using photolithography.

6. (5%) What diode is being reverse-biased when we tie the n-well to Vdd?

7. (15%) In the attached figure, show the cross-section down into the silicon along the horizontal yellow line.

8. (5%) What can happen when parasitic bipolar (NPN and PNP) transistors form in a CMOS chip?

9. (10 %) Give the main reason why contacts and vias have material extending beyond the cuts in the oxide layer.