EE477 - s09 lab3 part2

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 Part 2 Final Release

Module Design, Cadence and SPICE

Due 5/2/09 11:59 PM

There will be no extensions so plan your time accordingly

This lab addresses the design of a special-purpose circuit. The basic building block in the circuit is a very simplified digital neuron that you built in Lab 3 Part 1. You will build a small network with this neuron and inverter as basic building blocks in this part of Lab 3. In the writeup below, I am referring to the most significant bit of data as A2 and B2, and least significant bit as A1 and B1.

The "Quarterback" Neural Network

First, layout your neuron and simulate just as you did your neuron circuit to be sure it functions correctly.

For the project, you are to assemble a "neural net" using 4 of these neurons. The network is designed to tell a football quarterback to pass (throw) the football only under certain conditions. You do not have to understand the game of football to work this lab perfectly. We will tell you all the inputs, conditions, and outputs.

Operation of the Neural Network:

The central quarterback neuron that provides the output throw signal has five inputs, 4 excitatory and one inhibitory. The first input is PPC (A1) (pass play called), meaning that he is to throw the ball on this play if possible. The second input is PCR (B1) (pass completed ratio) meaning that he has completed many passes successfully in the past, and the third input is TA (B2) (try anything). The fourth input is RDF (A2) (receiver down field) meaning there is an eligible receiver (player on his team) downfield. The inhibitory input is NOTRWC (receivers well covered) meaning that defenders from the other team are close to the receivers and they could intercept the ball. Note that this input is inverted so it can be asserted low.

The second neuron is the TA neuron. The first excitatory input is PPC (A2) . The second input is CRD (A1) (clock running down)( meaning time is almost out and he should try anything. The third input is ABS (B2) (about to be sacked) meaning that he is about to be tackled and should get rid of the ball if possible. The fourth input is TIW (B1) (team is winning). The inhibitory input is tied high.

The third neuron is the RDF neuron. It checks whether receivers are downfield to catch the ball. The excitatory inputs to the RDF neuron are PPC (A2), R1DF (A1), R2DF (B2) , and R3DF (B1). The inhibitory input to the RDF neuron is tied high.

The fourth neuron is the RWC neuron. It checks whether defenders are with the receivers and could intercept (catch) the ball. It has excitatory inputs R1WC (A2), R2WC (A1), R3WC(B2) and QIH (B1) (quarterback has thrown lots of interceptions). The inhibitory input to the RWC neuron is NOTABS. You must generate NOTABS from ABS.

There are 12 primary inputs: PPC, PCR, CRD, ABS, TIW, R1DF, R2DF, R3DF, R1WC, R2WC, R3WC and QIH. There are 3 intermediate outputs TA, RDF and RWC, and three control inputs, load, reset and clock/notclock. You can't test all combinations of the inputs. Load should be kept high for all cycles. Clock cycle 1 is the period when the clock is low followed by the clock high.

In clock cycle 1, reset all neurons. All other inputs except load should be low. Throw should be low at the end of the clock cycle.

In clock cycle 2, Unassert reset for the rest of the clock cycles. set all primary inputs except load low. Throw should be low.

In clock cycle 3, set PPC, Load and PCR high, and all other primary inputs low. Throw should be low.

In clock cycle 4, set PPC, PCR, R1DF, R2DF high, and all other primary inputs except Load low. Throw should be low and RDF should be high at the end of the clock cycle.

In clock cycle 5 hold inputs steady. Throw should be high and RDF should be low.

In clock cycle 6 hold inputs steady except R1WC, QIH and R2WC high. Throw should be low. RDF and RWC should be high.

In clock cycle 7, set PPC, PCR, R1DF and R2DF high, R1WC, QIH and R2WC high, and all other primary inputs except Load low. Throw, RDF and RWC should be low.

In clock cycle 8, set PPC, PCR, R1DF, CRD, ABS and R2DF high, R1WC, QIH and R2WC high, and all other primary inputs except Load low. Throw and RCW should be low. RDF, and TA should be high.

In clock cycle 9, hold inputs steady. Throw should be high, and RDF, RWC and TA should be low.

In clock cycle 10, set PPC, PCR, CRD, and ABS high and all other primary inputs except Load low. Throw should be low. TA should be high.

In clock cycle 11, hold inputs steady. Throw should be high. TA should be low.

In clock cycle 12, hold inputs steady. Throw should be low. TA should be high.

Design Requirements:

You can use any combination of multiple clocks you wish, but only clock and /clock are clock inputs to the circuit and you will have to design circuits to generate the other clocks. /load is not an input to the circuit. You need to generate it if you need it. You can assume reset is asserted low if you like.

You should use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells or the transistor sizes unless the rise/fall times do not meet the requirements of lab 1. However, you can modify the layout in minor ways if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Make sure your ohmic contacts meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course they should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts.

You can use metal layers 1, 2 and 3 for the neuron. You can use metal layers 1-5 for the entire neural network.

The diagram below shows how the neurons are to be connected.

The Laboratory Design Goal

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.

The Laboratory Steps For the Neural Network

1. Design your circuit and create a Cadence circuit (schematic) diagram and a Cadence layout using the cells you have already designed. You cannot design new cells for Lab 3. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram for your neuron. Use LVS to verify your layout prior to SPICE simulation. Important note: Any pins in your layout labeled the same should be physically connected.

2. Simulate your schematic and layout with SPICE to ensure that your design works correctly The inputs, intermediate outputs and final output to your project circuit should be named exactly as we have named them here. It is important you follow this naming convention so we can verify that your circuit works. You will not be able to simulate all possible inputs. Choose your cases wisely if you decide to simulate more cases than those required.

3. The delay you should measure with SPICE is the clock cycle. The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design and report it clearly so we can find it.

4. Upload your report to the assignments function of Blackboard, incliding your layout and simulation files as a TAR file so that we can test (simulate) your circuit to be sure it performs as specified Be sure to include your SPICE input files for the project. The report should be a pdf file.

Lab Report Contents:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number.
Your neuron layout and neuron layout simulation results.
A description of the network you built, including a gate or transistor level circuit diagram printed from Cadence.
The neural network layout screen capture.
A description of the simulation experiments you ran with SPICE for the network.
SPICE netlist files generated by Cadence, which will include the technology file, the input stimulus file and the circuitry netlist.
SPICE outputs for the neural network schematic and layout as shown in MWAVES images. Use different panels to show these signals. Put PPC, PCR, CRD, ABS, TIW, and QIH in one panel , and R1DF, R2DF, R3DF, R1WC, R2WC, R3WC in one panel, and TA, RDF, RWC, clock, load, reset, and THROW in one panel. Print each panel on a separate page. To print multiple panels into separate pages, inside MWAVES Print Window, select
All panels, and One Panel per page. You will need to submit 3 pages of waveforms (in stacked mode) for each simulation.

Items 1-5 and 7 should all be in a single report. Tar this report along with the files specified in item 6, and upload to the assignments page of the blackboard.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.