EE477 - s07 lab3

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3

Module Circuit Design, Layout and SPICE

Due April 27, 2007, 12:00 Midnight

This lab addresses the design of a special-purpose circuit. The basic building block in the circuit is a very simplified digital neuron. You will build a small network with this neuron as a basic building block.

The digital neuron

There are four data inputs to the neuron, A, B, C, and D, load, reset, and a clock. You can assume /clock is an input too but you need to generate other inverted inputs. The neuron contains a flip flop, and the output of the flip-flop represents the output of the neuron. The neuron "fires" when 3 of the 4 inputs are high, and after the positive edge of the clock, the output of the flip-flop goes from low to high. After the next rising clock, the flip-flop output falls. The neuron cannot "fire" two clock cycles in a row. Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance. A block diagram of the neuron is shown below.

The Neural Network

For the project, you are to assemble a "neural net" using 6 of these neurons.

You can use any combination of multiple clocks you wish, but only clock and /clock are inputs to the circuit and you will have to design circuits to generate the other clocks. /load is not an input to the circuit. You need to generate it if you need it. You can assume set and reset are asserted low if you like.

You should use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells or the transistor sizes unless the rise/fall times do not meet the requirements of labs 1 and 2. However, you can modify the layout in minor ways if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Make sure your ohmic contacts meet the following requirement: include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts.

The diagram below shows how the neurons are to be connected.

The Laboratory Goal

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.

The Laboratory Steps

1. Design your circuit and create a Cadence circuit diagram and a MAGIC layout using the cells you have already designed. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram for your neuron.

2. Simulate your circuit and layout with SPICE to ensure that it works logically. The inputs to your project circuit should be named clock, load, red, yellow, round, cylindrical, small, large, green, purple, sweet and reset. The output should be named apple. It is important you follow this naming convention so we can verify that your circuit works.

Use the following sequence of inputs (See timing diagram below for exact details):

a) Reset all flip flops (even though reset is shown asserted high you could assert it low) using whatever clock settings you need. This will vary depending on how you implemented reset.

b) Set load, red, yellow, large (wait til the second cycle for large to become high), round and sweet to 1. Set load high. All other inputs should be 0. Clock the circuit three times. Your output apple should be high after the third upward transistion of the clock.

c) Now lower red, yellow, large, and raise green, purple and small. Leave round and sweet high. Now your output should be low after three positive clock edges.

d) Now hold your load input low. Return to the inputs in part b. After three clock cycles, the output should remain low.

3. Simulate your circuit with SPICE. The delay you should measure with SPICE is the clock cycle. The faster your clock cycle, the faster your circuit will function.

4. Measure the area of your design in square lambda using the b command in MAGIC. Compute the area-delay product of your design. Be sure you convert microns to lambda in order to get credit for this part of the lab.

5. Upload your report to the digital drop box, incliding your magic and simulation files as a zip file so that we can test (simulate) your circuit to be sure it performs as specified Be sure to include your SPICE files for the project.

Testing Strategy

Here is a testing strategy that might be useful to you: Build the majority gate in Cadence and test it using SPICE. Add the flip flop and any logic needed to keep the flip flop from firing two clock cycles in a row. Test the entire "neuron." Now create your neural network in Cadence and test it. Use the same incremental strategy to perform your layout in MAGIC and to test your layout.

Timing Diagram

Lab Report Contents:

1.Title page

2.Discussion and explanation of how your design works.

3.Block diagram of your design and logic/gate level diagram - Cadence diagrams are fine

4.Floorplan (where each cell is on your layout) - This is a sketch of how you arranged your neurons on your layout. It can be hand drawn and scanned.

5.SPICE outputs for your Cadence circuit and your MAGIC layout.

6.Layout of the neuron and of the 6-neuron network

7.Area-delay product