EE477 - s07 lab2

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2

Latch/FF Design, SPICE and IRSIM

Due April 6, 2007 4:00 PM

This laboratory uses SPICE model parameters supplied by MOSIS. V_dd = 2.5 v.

Part 1: Cell SPICE Simulations

Simulate the cells you designed in Lab 1 using SPICE, attaching the inverter cell as a "load" to the output of each cell. Use the same inputs in the same order as you did for the IRSIM simulations. Use the device sizes you were instructed to use in Lab 1. You can use these values for transistor betas: β_n (beta)= 219.4 W/L μ A(microamps)/V²and β_p (beta)= 51 W/L μ A/V². Note the rise and fall times at the outputs of each cell. Use a rise and fall time for the inputs signals of .1 ns.

This part of your lab report should contain a title page, a list of all the cells you simulated, and the SPICE simulation outputs. Also include a discussion of cell rise and fall times and a comparison to the simulation results you got for Lab 1. On-campus students should turn in hard copies of the Part 1 report.

Part 2: LATCH and FLIP-FLOP DESIGN

1. Use the cells you have already constructed to design a latch, and use two latches to build a CMOS D flip-flop in Cadence. Assume the flip-flop is clocked, and that clock, /clock, synchronous load and synchronous /load are inputs to your design. You must include asynchronous set and reset signals in your circuit. Load is active high. The flip-flop should be positive edge triggered. The clock signal should not be gated (in other words, the clock signal should not pass through any logic gates before arriving at the flip-flop).

The transistors in the flip-flop should be sized as they were to be sized for Lab 1. Do not use ratioed (pseudoNMOS) logic (not covered in this class). Do not use dynamic logic or dynamic storage (not covered yet).

2. Simulate the flip-flop you built in Cadence, again assuming the data D, clock, /clock, set, reset, load and /load signals are inputs to your design. Be sure to try all possible combinations of data inputs versus present state of the flip flop, using the waveforms shown below. Start with clock low, D low and load high. Be sure test set and reset as well. For the simulations, attach your inverter as a "load" to the flip-flop output. Adjust the timing of your clock to be as fast as possible and still have the circuit work properly. The waveforms shown below show the order of changes of inputs you are to use for the simulations. Set and reset are not shown and should be simulated with clock and load low.

3. Use the same layout methodology you used in Lab #1 to layout the flip flop, using only the bottom two layers of metal, metal 1 and metal 2.

Extract SPICE input files for the flip-flop layout and simulate with V_in (Data) varying from 0 v. to Vdd (2.5 v.) and then Vdd to 0 v. For the simulations, attach your inverter as a "load" to the flip-flop output. Again assume the clock and load signals are inputs to your circuit. Proper functioning includes having the low output be less than .1 V_dd and the high output being greater than .9 V_dd.The clock and all input signals should have a rise and fall time of .1 ns. Plot V_in and V_out versus time. Note the delay between V_inchanging and V_out changing. Use the definitions of delay given in the text as the time between the input achieving 50% of its final value and the output achieving 50% of its final value. The clock should have a 50% duty cycle. Make the clock as fast as you can and still get correct results.

What to turn in for Part 2: Your lab should contain the following items:

A cover sheet giving your name, date you submitted the lab, title, and student number.
A description of the flip-flop you built, including a transistor-level or gate-level circuit diagram printed from Cadence.
The flip-flop layout
A description of the simulation experiments you ran with SPICE
SPICE outputs for the flip-flop schematic and layout

On-campus students should turn in hard copies of the Part 2 report except for the layout.