University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #1

Logic Gate Layout and SPICE Experiments with Combinational Cells

Due 3/26/07, 4 PM

1. (20%) Use CADENCE Virtuoso to design complementary CMOS logic gates (cells) for the following functions: inverter, 2-input NAND, 3-input NAND, and a compound gate that implements the function G = NOT [ABC+ABD]. Design the cells at the transistor level.

2. (40%) Simulate your transistor circuits (Cadence circuits) using SPICE to determine that they function properly. Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A and B. Label your outputs INVOUT, NAND2OUT, etc. Show simulations of each gate with all possible combinations of inputs. Change the inputs in the following manner - ABC = 000, ABC = 001, ABC = 010....for the 3-input gate. For the 2-input gates AB = 00, AB = 01, etc. For the compound gate, follow the same type of input variations, starting with ABC = 000, and ending with ABC = 111. Please change the inputs in the order given so that we can grade what you are doing easily. Attach your inverter design to the output of each gate prior to circuit extraction and simulation to provide a load capacitance.

3. (40%) Layout your cells with MAGIC.

Transistor Sizes:

The NMOS transistors in the inverter should be "unit" transistor sized, as defined in the text and lectures, paying attention to the current design rules in the lab. For the inverter, widen the PMOS transistor channels as required so that the β's of the PMOS and NMOS transistors are about equal. You can use these values for transistor betas:


βn (beta)= 219.4 W/L μ A(microamps)/V2 and βp (beta)= 51 W/L μ A/V2

Remember that you can put two or more unit-sized transistors in parallel in place of widening a single transistor if it helps keep your methodology consistent. For the 2-input and 3-input NAND gates, adjust the rise and fall times to be equal in the worst case. For the compound gate, experiment with transistor widths that give equal output rise and fall times, in the worst case. This will be discussed in class Tues. March 6.

Design Methodology:

Use a uniform methodology to design all the gates, and only use metal1 and metal 2 for interconnect. Make sure that you minimize the use of poly (hint: you might only use poly around the gate region of each transistor). Your goal is to insure that it is easy to build more complex designs out of your gates, and to keep the cells small, with few layer changes for each connection. You want to extend your methodology to design compound gates as well. Keep in mind as you design the inverter that you may want to redesign it later with wider transistors. At this point in the semester, try to minimize the white space to create cells that are as small as possible, but easily combined into larger circuits. One hint: you can design the cells so that the output of each cell lines up exactly with an input of every cell type. The output and input can line up horizontally or vertically.

The following is one example of such a methodology:

"Design each cell to be the same height. Power and ground will be routed horizontally later, and the input to each cell should be vertical. The output should come out horizontally on the metal 2 layer. Use a style similar to the cells shown in Fig. 1.10 of the text."

This is only an example. Instead, you might choose to design each cell to be the same width, for example. You might route the inputs to the cell horizontally, and use different layer assignments than the example.


Turn in final transistor-level schematics, layouts and SPICE outputs for all gates .

Lab Report Contents:

  1. Title page
  2. Discussion and explanation of how you sized transistors.
  3. Description of your design methodology.
  4. Ttransistor schematics of gates
  5. Layouts of gates
  6. SPICE outputs for each gate
  7. Conclusions about the lab, especially about sizing the transistors in the compound gate.

You will be given instructions how to submit the lab report.