Figure 1:The inverter circuit
THE OUTPUT INTERCONNECT CAPACITANCE
The wire from the output of the inverter to the pad is on n+ then on the metal 1 layer. A short metal 1 strap connects p+ at the PMOS drain to the n+ diffusion. The output passes through 1 contact cut (diffusion-metal) at the output of the inverter from p+ to metal 1, one contact cut from metal 1 to n+ and 1 contact cut from n+ to metal 1.
1. We look at the output metal 1 pad as a capacitor, since there is a capacitance between the metal and the substrate below. We assume nothing else is under the metal pad. We assume a parallel plate model. Compute the capacitance of the metal pad. The metal pad is 100 lambda x 100 lambda. For the oxide thickness, you will need to convert angstroms to microns. Assume there is no fringing field capacitance, and that there is a double layer of oxide under the metal.
2. The metal connecting the inverter to the output pad is 4755 microns long, and 6 lambda wide. Compute the capacitance of the metal interconnect from the diffusion-metal contacts to the output pad. Use the same parallel plate model as problem 1, above. Assume there is no fringing field capacitance, and that there is a double layer of oxide under the metal..
THE OUTPUT CIRCUIT RESISTANCE
3. Compute the ß's of the NMOS and PMOS transistors using ßn (kn)= 219.4 W/L µ A(microamps)/V2 and ßp (kp)= 51 W/L µ A/V2
5. Compute the total resistance of the metal and diffusion interconnect running from the inverter to the output pad. The diffusion interconnect is 40 microns long, and 4 lambda wide. Assume the metal sheet resistance is .1 ohms/square, and the diffusion resistance is 40 ohms/square. Include the contact resistance at a typical value of 10 ohms/contact in your total.
5. Compare the total interconnect + contact resistance to the channel resistance of the PMOS transistor in the linear region. Assume the PMOS transistor is fully on. Can we neglect the pad resistance?
THE INPUT CIRCUIT RESISTANCE
The input to the inverter comes from off-chip as well. We must consider the capacitance and resistance of the input metal pad and interconnect, along with capacitance of the inverter gates. The metal 2 input pad is 45 X 45 microns.
6. Compute the resistance of the input metal interconnect.
7. Compute the resistance of the poly interconnect, assuming the poly is 3 lambda wide, and has not been silicided.
8. Compute the total resistence of the interconnect, including contacts and vias.
FRINGING FIELDS
9. Assume the output metal interconnect is subject to fringing fields. Use the curves shown in Fig. 6.18 to approximate the metal interconnect capacitance, including fringing fields.
NOISE MARGINS
10. An off-chip inverter using a special kind of CMOS circuit outputs a "high" signal when Vdd >=2 .1 v, and a "low" when Vdd <= .6 v. The on-chip inverter receiving the signal sees a high at a minimum of 1.9 v, and a low at a maximum of .9 v. If the noise signal has an amplitude swing of plus or minus .4 v., what will be the high noise margin? the low noise margin?
DELAY COMPUTATIONS
11. Solve the following NAND problems:
a) Solve for the βpeff (beta) of a 5-input NAND gate constructed of unit size devices.
b) Solve for the output rising and falling RC time constants when this NAND gate drives an inverter with unit size devices, assuming Cg(n or p) = 100 ff, Rchn = 500 ohms, Rchp = 1000 ohms and Cd (drain or source) = 40 ff for the individual transistors.
12. Using a chain of six inverters, assume each one can drive 2 times the capacitive load of the previous inverter. How big a load could be driven, assuming equal delay in all stages, and assuming Cg(n+p) for the first inverter in the chain = 50 ff.? You can assume Cd = Cgn = Cgp.
13. An inverter drives a long wire (10 mm) on a special kind of metal1 minimum width (3 lambda) to the input of another inverter. Both these inverters have identical unit size transistors. In order to speed up the circuit, Ernie Engineer inserts an identical inverter in the middle of the 10 mm wire. Ernie’s boss wants Ernie to insert an inverter in the middle of the wire that has transistors 3 times as wide as the other inverters.
• Assume the capacitance of each 5 mm section of the wire is 60 ff. Assume the special kind of metal1 has resistance .02 ohms per square.
• Assume Cg(n or p) = 100 ff, Rchn = 500 ohms, Rchp = 1000 ohms and Cd (drain or source) = 40 ff for the original inverters.
• Use equivalent circuits and the lumped RC time constants to show Ernie’s boss whether Ernie’s design is better than the boss’s design or not.
14. A 6-input NAND gate is constructed of unit-size devices. Resize the PMOS devices so that rise and fall times are approximately equal.
15. Set up the integral equations to compute the fall time at the output of an inverter, assuming fall time is defined as the time it takes the output to fall from 95% to 5% of it’s initial value. Explain the region or regions of operation of both the transistors in the inverter when the output is falling. What assumptions are we making about the input to the inverter in order to do this analysis?
Problems 16 - 18 will be posted tomorrow.
