A. Parker EE 477L Spring 2007

Homework Assignment #3Due by 12:30PM 2/13/07 *

1. (25 %) Use the compound gate from Assignment #2 problem 2 as an example. Design a similar compound gate that is a majority gate with 4 inputs (output high when 3 of the 4 inputs are high). Note that you would need an inverter at the output to make the output high when 3 inputs are high but there is no need to show this inverter in detail. Label the sources and drains of all transistors. Show an identical Euler path for both NMOS and PMOS transistors by listing transistor inputs on both paths.

2. (5 %) State one thing you learned from the fabrication video that was not discussed in class.

3. (10 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = .5 v. and Vout = 2.0 v. Both transistors are "on".

4. (5 %) Why would we tie an n+ diffusion in an n-well to Vdd?

5. (10 %) What method do we use to create contact cuts in an integrated circuit as it is being fabricated? Be sure you give all relevant steps.

6. (10 %) Bipolar transistors are one kind of parasitic device that can cause circuit problems in CMOS. Where would we find parasitic MOS transistors?

7. (5 %) Design rules governing the spacings between features help us avoid major failure. Are we interested in the maximum spacings or minimum spacings to avoid failure?

8. (20 %) Show a side view (down into the substrate) of the attached figure, assuming we slice vertically into the picture, perpendicularly to the red line, along the black line. You should only show features that fall directly under that line.You can see the MAGIC layer colors.

9. (5 %) Why is metal1 fabricated after diffusion in a typical CMOS process?

10. (5%) What are stacked contacts?

* You may turn in the homework in class, regular DEN, or in the digital drop box. Late homework can be submitted under my door.