Homework Assignment #2

EE 477 Spring 2007 Professor Parker

Due Midnight 1/30/06 in class or email/fax to den

1. (20%) The increment computation shown in the lecture is performed using complementary NAND/NOR/INVERT circuitry (See Fig. 1). Use the same style of design (use only NAND, NOR, INVERT gates) to build a transistor-level circuit that implements a majority gate with 5 inputs. The output is high if any 3 of the inputs are high.

You can assume the complements of the inputs also to be inputs to the circuit. You can use gates with any number of inputs.

2. (20%) The decrement computation shown in the lecture is a compound gate (See Fig. 2).

a) Redesign your circuit from Problem 1 at the transistor level using a compound gate. Show the compound gate transistor diagram. Compare the number of transistors to the original design in Problem 1.

b) Now redesign your circuit from Problem 1 at the transistor level using only NOR gates. Again compare the transistor count. Show your work. You can use gates with any number of inputs.

3. (15%) Design a level-sensitive latch at the transistor level that contains a NOR gate in the forward path and and a NAND in the feedback path where an inverter is shown in the lecture notes. Can your latch be set or reset asynchronously? Show the transistor circuit diagram. Use NAND, NOR and INVERT gates for the mux at the input to the latch.

4. (10%) For your latch in Problem 3, you had to design a multiplexer to select between one of two inputs using only NAND, NOR and INVERT complementary CMOS gates. Does your design use more transistors than a mux built with transmission gates?

5. (20%) Sketch a stick diagram of the transmission gate mux mentioned in Problem 4. You do not need to use the cell design method shown in class for this exercise.

6. (15%) Use Cadence schematic capture to draw a schematic of your design from problem 1. Capture your schematic using a "print screen" (PC) or "Grab" (MAC).