Homework Assignment #4 Spring 2006 EE 477

Due April 13, 2006, 3 PM

Edited 4/4/06 - changes are shown below in bold red text.

This assignment is worth 1.5 regular assignments

The problems in this assignment focus on an inverter. The inverter input is on minimum-width metal 2 for 9805 microns, then goes through a via and contact to reach poly, then on poly for 150 microns, including the gates. The poly is minimum width. The inverter output is on diffusion for 200 microns then goes through a contact to metal 1, and the metal 1 output goes to an output pad on the chip. The inverter is shown below. The gate of the NMOS transistor in the inverter is two times unit size width, and unit size channel length, and the gate of the PMOS transistor is sized so that theNMOS and PMOS transistor betas are exactly equal. lambda is .125 microns. Assume Vdd is 2.5v. Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .5 microns.

Figure 1:The inverter circuit

THE OUTPUT CIRCUIT CAPACITANCE

The wire from the output of the inverter to the pad is on n+ then on the metal 1 layer. A short metal 1 strap connects p+ at the PMOS drain to the n+ diffusion. The output passes through 1 contact cut (diffusion-metal) at the output of the inverter from p+ to metal 1, one contact cut from metal 1 to n+ and 1 contact cut from n+ to metal 1.

1. We look at the output metal 1 pad as a capacitor, since there is a capacitance between the metal and the substrate below. We assume nothing else is under the metal pad. We assume a parallel plate model. Compute the capacitance of the metal pad. The metal pad is 45 microns x 45 microns. You will need to convert angstroms to microns. Assume there is no fringing field capacitance, and that there is a single layer of oxide under the metal..

2. The metal connecting the inverter to the output pad is 4755 microns long, and three times minimum width. Compute the capacitance of the metal interconnect from the diffusion-metal contacts to the output pad. Use the same parallel plate model as problem 1, above. Assume there is no fringing field capacitance, and that there is a single layer of oxide under the metal..

3. Compute the capacitance of the drain diffusion contributed by both the NMOS and PMOS transistors. Use the equation given in the lecture to compute the capacitance. Use Cjbsn = 17.27 x 10-4 pF/ µm2 and Cjbswn = 4.17 x 10-4 pF/ µm (micrometer) and

Cjbsp = 18.8 x 10-4 pF/ µm2and Cjbswp = 3.17 x 10-4 pF/ µm (micrometer). ( You may have to do problem 5 first to do this problem.)

4. Total the capacitance contributed by the transistor drains, interconnect, and output pad.

THE OUTPUT CIRCUIT RESISTANCE

5. Compute the ß's of the NMOS and PMOS transistors using ß_n (k_n)= 219.4 W/L µ A(microamps)/V2 and ß_p (k_p)= 51 W/L µ A/V2

6. Compute the total resistance of the metal and diffusion interconnect running from the inverter to the output pad. Assume the metal sheet resistance is .1 ohms/square, and the diffusion resistance is 40 ohms/square. Include the contact resistance at a typical value of 10 ohms/contact in your total.

7. Compare the total interconnect + contact resistance to the channel resistance of the PMOS transistor in the linear region. Assume the PMOS transistor is fully on. Can we neglect the pad resistance?

THE INPUT CIRCUIT RESISTANCE AND CAPACITANCE

The input to the inverter comes from off-chip as well. We must consider the capacitance and resistance of the input metal pad and interconnect, along with capacitance of the inverter gates. The metal 2 input pad is 45 X 45 microns.

8. Compute the capacitance of the interconnect (metal and poly), assuming no fringing fields.

9. Compute the gate capacitance of the two transistors that make up the inverter.

10. Compute the total capacitance of the input circuit (sum of the pad, gate and interconnect capacitance on the input side).

11. Compute the total resistence of the interconnect, including contacts and vias.

FRINGING FIELDS

12. Assume the output metal interconnect is subject to fringing fields. Use the curves shown in Fig. 6.18 to find the metal interconnect capacitance, including fringing fields.

NOISE MARGINS

13. An off-chip inverter using a special kind of CMOS circuit outputs a "high" signal when Vdd >= 2.2 v, and a "low" when Vdd <= .5 v. The on-chip inverter receiving the signal sees a high at a minimum of 1.9 v, and a low at a maximum of .9 v. If the noise signal has an amplitude swing of plus or minus .4 v., what will be the high noise margin? the low noise margin?