A. Parker EE 477L Spring 2006

Homework Assignment #2Due by 5 PM 2/8/06 *

1. (15 %) Construct a compound gate at the transistor level that performs the function Z= NOT([XY]+[TU + V] [W + S]). Label the sources and drains of all transistors.

2. (5 %) What could happen if we don't tie the substrate in an integrated circuit to Gnd?

3. (10 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = 2.5 v. and Vout = 2.0 v. Both transistors are "on".

4. (5 %) Why would we have an n+ diffusion in an n-well?

5. (5 %) What method do we use to remove material from an integrated circuit as it is being fabricated?

6. (10 %) Bipolar transistors are one kind of parasitic device that can cause circuit problems in CMOS. What would be a symptom of this problem?

7. (5 %) Design rules governing the spacings of features help us avoid which major failure?

8. (20 %) Show a side view (down into the substrate) of the attached figure, assuming we slice horizontally, as shown in the red line . You should only show features that fall directly under that line.

9. (5 %) What major problem could occur when poly is fabricated after diffusion in a typical CMOS process?

10. (10 %) What is the next step in fabricating a metal2 layer, assuming that the photoresist has been applied and exposed to UV light, and the exposed photoresist removed. Assume a positive process.

11. (10 %) How do we connect the top metal layer (metal 5) to poly?

* You may turn in the homework in class, regular DEN, or in the box labeled EE 477L in EEB 106. Late homework can be submitted under my door.