Homework Assignment #1

EE 477 Spring 2006 Professor Parker

Due 4:30 PM 1/30/06 in EEB 106

Remote students: If you do your assignments in color, you can email rather than fax them.

1. (15%) The increment computation shown in the lecture is performed using complementary NAND/NOR/INVERT circuitry (See Fig. 1). Use the same style of design (use only NAND, NOR, INVERT gates) to build a transistor-level circuit that implements the Boolean equation

/G = [(A+B) * (C+D)] * [/E + /F + /H]

/ means "not". You can consider A, B, C, D, E, F, H and their complements inputs to the circuit. You can use gates with any number of inputs.

2. (30%) The decrement computation shown in the lecture is a compound gate (See Fig. 2).

a) Redesign your circuit from Problem 1 at the transistor level using a compound gate. Show the compound gate transistor diagram. Compare the number of transistors to the original design in Problem 1.

b) Now redesign your circuit from Problem 1 at the transistor level using only NAND gates. Again compare the transistor count. Show your work. You can use gates with any number of inputs.

3. (15%) Design a level-sensitive latch at the transistor level that contains a NOR gate in the forward path and and inverter in the feedback path where an inverter is shown in the lecture notes. Can your latch be set or reset asynchronously? Show the transistor circuit diagram.

4. (20%) Design a multiplexer to select between one of three inputs using only NOR and INVERT complementary CMOS gates. Does your design use more transistors than a mux built with transmission gates?

5. (20%) Sketch a stick diagram of your mux designed for Problem 4. You do not need to use the cell design method shown in class for this exercise.