A. Parker EE 477L Spring 2005

Study Problem Solutions

1. Use Equation 2.45 given in the text on p. 103. You are to compute beta given the channel resistance and Vgs. Vtn is given on p. 1 of the study problems. Your answer should be about 1650 microamps/volt squared. This number is not realistic for our technology, but makes sense in this artificial problem, where the channel resistance is pretty small considering that the transistor is not completely turned on (Vgs << Vdd).

2. The equivalent circuit contains one p-type diffusion area, one n-type diffusion area, and the output terminates on two transistors, one n-type and one p-type.

The total capacitance is 25+26 fF (diffusion cap's) + 29 fF (gate cap of the following gate) = 80 fF

3. First, note that the gate has minimum size devices. Thus the transistor widths are 3 lambda, not 4. An inverter built with the minimum width instead of unit size device would have 3/4 the width, and therefore 3/4 the beta. Now in a 4-input NOR gate, we have 4 pmos transistors in series. Therefore the effective beta would be betap/4. So the final effective beta would be 3/16 * betap, where betap is the beta of a unit size pmos transistor.

4. The inverters have been altered by widening the transistors by a factor of 3. Therefore the second inverter in the chain has transistors 3 times as wide as the first inverter, and the third inverter has transistors 9 times as wide as the first inverter.

5. Solution still being developed.

6. In a 3-input NOR gate, there are three PMOS transistors in series. To get equal rise and fall time in an inverter, we need to multiply the width of the P transistor by 4. (see the betas on the first page of the study problems). Now we have 3 transistors in series, so to get the equivalent beta of a single PMOS transistor we have to multiply the widths by 3. So, in order to get equal rise and fall times, we need to multiply the PMOS transistor widths by 3 x 4 = 12.

7. The transmission gate adds resistance to the output circuit (channel resistance of a pmos transistor in parallel with an nmos transistor), and capacitance (diffusion capacitance of the sources and drains of both transistors). Note that, depending on the data being transferred, the channel resistance can vary significantly.