University of Southern California
Department of Electrical Engineering - Systems
EE 477 Laboratory #3
Module Design, IRSIM and SPICE
Laboratory #3 Due April 29, 2004, 4:00 PM
Revised 4/16/05
This lab addresses the design of a special-purpose circuit. The circuit is an abacus-like counter. The counter counts from 0-10, and then resets the abacus to 0. Shown below is the counting sequence. 1 indicates the presence of a bead and 0 indicates the absence of a bead. The beads representing 5's are to the left of the bar, and the ones representing 1's are to the right. The number to the left of the abacus beads indicates the state number. A flip flop should store each bead position's contents.
state 5's 1's count
0. 011 | 011111 (0)
1. 011 | 101111 (1)
2. 011 | 110111 (2)
3. 011 | 111011 (3)
4. 011 | 111101 (4)
5. 011 | 111110 (5)
6. 101 | 011111 (5)
7. 101 | 101111 (6)
8. 101 | 110111 (7)
9. 101 | 111011 (8)
10.101 | 111101 (9)
11.101 | 111110 (10)
12.110 | 011111 (10)
13.011 | 011111 and carry out
The inputs to the circuit are count, reset and clock. The outputs are the 9 bits representing the beads, and a carry out signal.
When the circuit starts up, the beads are set to the zero position 011 | 011111. Count is asserted for 5 clock ticks, producing states 1-5. The 6th clock is used to change from one representation of 5 to another, producing state 6. Count is again asserted for 5 clock ticks, producing states 7-11. The 12th and 13th clocks are used to change between representations of 10, producing states 12 and 13. Count is guaranteed to be low when the systems is in state 5, 11, or 12. The 14th clock the count begins again. You should be able at any clock cycle except states 5, 11,or 12 to recognize when Count is low and not increment the data stored. The circuit enters state 1 from either state 13 or state 0. When the circuit has reached state 13, it should go to state 1 on the next clock that also has count asserted.
You can use any combination of clocks you wish, but only clock and count are is inputs to the circuit and you will have to design circuits to generate the other clocks. You should use the cells you designed in labs 1 and 2 to build your circuit. You can change transistor sizes in your cells. Do not change the circuit structure of your cells. However, you can modify the layout in minor ways if you can see some ways to make the circuits smaller or faster. Make sure your ohmic contacts meet the following requirement: at least two contacts per 50x50 lambda, one for psubstrate and the other for nwell. Every separate block of nwell should have at least one ohmic contact.
For this lab, you can use any layout strategy you choose. The goal is to minimize the area·delay (the product of area and delay). Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.
1. Design your circuit and create a MAGIC layout using the cells you have already designed. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram.
2. Simulate your layout with IRSIM to ensure that it works logically. Set up the inputs so that you test the circuit completely. In the rare event that IRSIM does not work, you can omit this step, but remember to turn in the failed IRSIM output. If IRSIM fails, you can use another simulator if you are familiar with one. Check with your TA before doing this to be sure the TA can help you if there are difficulties.
3. Simulate your circuit with SPICE. The delay you should measure with SPICE is the clock cycle. The faster your clock cycle, the faster your circuit will function. The inputs should be named clock and count. The outputs should be named BP1, BP2,..., BP9 (for the 9 bead positions, lowest/rightmost one is BP1 and highest/leftmost one is BP9) and carryout. It is important you follow this naming convention so we can verify that your circuit works.
4. Measure the area of your design in square lambda. Compute the area-delay product of your design. Be sure you convert microns to lambda in order to get credit for this part of the lab.
5. Email the SPICE file to parker@eve.usc.edu so that we can test your circuit to be sure it performs as specified.
Lab Report Contents:
1.Title page
2.Discussion and explanation of how your design works.
3.Block diagram of your design and logic/gate level diagram
4.Floorplan (where each cell is on your layout)
5.IRSIM and SPICE outputs for your design.
6.Layout
7.Area-delay product