University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2

Latch/FF Design, SPICE and IRSIM

Part 1: Due April 1, 3:00 PM

Part 2: Due April 14, 4:00 PM

This laboratory uses SPICE model parameters supplied by MOSIS. Vdd = 2.5 v.

Part 1: Cell SPICE Simulations

Simulate the cells you designed in Lab 1 using SPICE. Use the same inputs in the same order as you did for the IRSIM simulations. Use the device sizes you were instructed to use in Lab 1. You can use these values for transistor betas: βn (beta)= 219.4 W/L μ A(microamps)/V2 and βp (beta)= 51 W/L μ A/V2 or you can use a more realistic ratio βn (betan)/βp (betap) = 2. Note the rise and fall times at the outputs of each cell.

This part of your lab report should contain a title page, a list of all the cells you simulated, and the SPICE simulation outputs. Also include a discussion of cell rise and fall times. On-campus students should turn in hard copies of the Part 1 report.

Part 2: LATCH and FLIP-FLOP DESIGN

1. Use the cells you have already constructed to design a latch, and use two latches to build a CMOS D flip-flop. Use the same layout methodology you used in Lab #1, using only the bottom two layers of metal. Assume the flip-flop is clocked, and that clock, /clock, synchronous load and synchronous /load are inputs to your design. You must include asynchronous reset and set signals in your circuit. Load is active high. The flip-flop should be negative edge triggered. The clock signal should not be gated (in other words, the clock signal should not pass through any logic gates before arriving at the flip-flop).

The transistors in the flip-flop should be sized as they were to be sized for Lab 1. Do not use ratioed (pseudoNMOS) logic (not covered in this class). Do not use dynamic logic or storage (not covered yet).

2. Simulate the flip-flop with IRSIM, again assuming the clock, /clock, load and /load signals are inputs to your design. Be sure to try all possible combinations of inputs versus present state. Start with clock high, D low and load high. Be sure to test set and reset as well.

Lab #2:

Waveforms for the test inputs:

clock ‾‾‾‾‾‾‾‾‾|______|‾‾‾‾‾‾‾‾‾|______|‾‾‾‾‾‾‾‾‾|______|‾‾‾‾‾‾‾‾‾|______|‾‾‾‾‾‾‾‾‾|__

data ____________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾

load ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|____________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|________

out XXXX_____________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________

(expected)

3. Extract SPICE input files for the flip-flop and simulate with Vin varying from 0 v. to Vdd (2.5 v.) and then Vdd to 0 v. Again assume the clock and load signals are inputs to your circuit. Adjust the timing of your clock to be as fast as possible and still have the circuit work properly. Proper functioning includes having the low output be less than .2 Vdd and the high output being greater than .8 Vdd. The clock and all input signals should have a rise and fall time of .1 ns. Plot Vin and Vout versus time. Note the delay between Vin changing and Vout changing. Use the definitions of delay given in the text as the time between the input achieving 50% of its final value and the output achieving 50% of its final value. The clock should have a 50% duty cycle.

What to turn in for Part 2: Your lab should contain the following items:

  1. A cover sheet giving your name, date you submitted the lab, title, and student number.
  2. A description of the flip-flop you built, including a transistor-level circuit diagram.
  3. The flip-flop layout
  4. A description of the experiments you ran with IRSIM and SPICE
  5. IRSIM and SPICE outputs for the flip-flop

On-campus students should turn in hard copies of the Part 2 report.