The following is one example of such a methodology:
"Design each cell to be the same height. Power and ground will be routed horizontally later, and the input to each cell should be vertical. The output should come out horizontally on the metal 2 layer. Use a style similar to the cells shown in Fig. 1.62 of the text."
This is only an example. Instead, you might choose to design each cell to be the same width, for example. You might route the inputs to the cell horizontally, and use different layer assignments than the example.
2. Simulate your cells using IRSIM to determine that they function properly. Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A and B. Label your outputs INVOUT, NAND2OUT, etc. Show simulations of each gate with all possible combinations of inputs. Change the inputs in the following manner - ABC = 000, ABC = 001, ABC = 010....for the 3-input gate. For the 2-input gates AB = 00, AB = 01, etc. For the transmission gate, label the control input S and vary the control input from 0 to 1 and back to 0. Change the input to the gate, A, 0 to 1 and back to 0 when S is low and again when S is high. Please change the inputs in the order given so that we can grade what you are doing easily.
Turn in final layouts for all gates and IRSIM outputs.
Lab Report Contents:
- Title page
- Discussion and explanation of how you sized transistors.
- Description of your design methodology.
- Layouts of gates
- IRSIM outputs for each gate
- Conclusions about the lab, especially about sizing the transistors in the XOR gate.
You will be given instructions how to submit the lab report.
University of Southern California
Department of Electrical Engineering - Systems
EE 477 Laboratory #1
Logic Gate Layout and IRSIM Experiments with Combinational Cells
Due 3/22/05, 4 PM
1. Use MAGIC to design complementary CMOS logic gates (cells) for the following functions: inverter, 2-input NAND and XOR, 3-input NAND, and transmission gate.
Transistor Sizes:
The NMOS transistors in the inverter should be "unit" transistor sized, as defined in the text and lectures. For the inverter, widen the PMOS transistor channels as required so that the channel resistances of the PMOS and NMOS transistors (as computed by Eq. 2.45) are about equal. You can use these values for transistor betas:
βn (beta)= 219.4 W/L μ A(microamps)/V2 and βp (beta)= 51 W/L μ A/V2
Remember that you can put two or more unit-sized transistors in parallel in place of widening a single transistor if it helps keep your methodology consistent. For the 2-input and 3-input NAND gates, use unit-sized NMOS and PMOS transistors. For the XOR gate, experiment with transistor widths that give equal output rise and fall times. The transistors in the transmission gate should be unit size.
Design Methodology:
Use a uniform methodology to design all the gates, and only use metal1 and metal 2 for interconnect. Make sure that you minimize the use of poly (hint: you might only use poly around the gate region of each transistor). Your goal is to insure that it is easy to build more complex designs out of your gates, and to keep the cells small, with few layer changes for each connection. Keep in mind also that you might want to extend your methodology to design compound gates as well. Your transmission gate and XOR gate might or might not be exactly the same methodology as your other cells. Keep in mind as you design the inverter that you may want to redesign it later with wider transistors. At this point in the semester, try to minimize the white space to create cells that are as small as possible. One final requirement: Design the cells so that the output of each cell lines up exactly with an input of every cell type. The output and input can line up horizontally or vertically.
The circuit for the XOR gate is shown here:
The following is one example of such a methodology:
"Design each cell to be the same height. Power and ground will be routed horizontally later, and the input to each cell should be vertical. The output should come out horizontally on the metal 2 layer. Use a style similar to the cells shown in Fig. 1.62 of the text."
This is only an example. Instead, you might choose to design each cell to be the same width, for example. You might route the inputs to the cell horizontally, and use different layer assignments than the example.
2. Simulate your cells using IRSIM to determine that they function properly. Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A and B. Label your outputs INVOUT, NAND2OUT, etc. Show simulations of each gate with all possible combinations of inputs. Change the inputs in the following manner - ABC = 000, ABC = 001, ABC = 010....for the 3-input gate. For the 2-input gates AB = 00, AB = 01, etc. For the transmission gate, label the control input S and vary the control input from 0 to 1 and back to 0. Change the input to the gate, A, 0 to 1 and back to 0 when S is low and again when S is high. Please change the inputs in the order given so that we can grade what you are doing easily.
Turn in final layouts for all gates and IRSIM outputs.
Lab Report Contents:
- Title page
- Discussion and explanation of how you sized transistors.
- Description of your design methodology.
- Layouts of gates
- IRSIM outputs for each gate
- Conclusions about the lab, especially about sizing the transistors in the XOR gate.
You will be given instructions how to submit the lab report.
