A. Parker EE 477L Spring 2005
Homework Assignment #3
Due 2/17/05 4 PM in EEB 106
Assume for the problems below that Vdd = 2.5 v, Vtp is -.6 v. and Vtn is .6 V.
1. A Boolean equation for computing a function of a 4-bit value is shown below:
P =(L+[/M])N + (M[/N]+L)[/K]
(a) (15%) Start by drawing the transistor level diagram for a compound gate to compute NOT(P), without simplifying the equation. Assume you have both true and inverted values of M, N and K as inputs .
The goal is to find an Euler path for the gate that is the same for both PMOS and NMOS transistors. You might be able to find one on the original circuit but you may need to rearrange the circuit by manipulating the Boolean equation so that you have an Euler path. At least one exists.
(b) (25%) Create a stick diagram from the Euler path, showing PMOS and NMOS diffusion areas, poly, and metal. Put vertical metal connections on metal 1, and horizontal ones on metal 2, including Vdd and Gnd. Use the methodology shown in lecture and in the text for the stick diagram. Use purple for metal 2.
2. (10 %) A PMOS transistor has VDS = -1.5 V. If the transistor is in the linear region of operation, what are the possible values of VGS?
3. (10 %)An NMOS transistor has VGS =.7 V , VDS = 1.1 V. What region of operation is it in? Now assume VGS = 1.3 V and VDS = 2 V. What region of operation is the transistor in?
4.(10 %) We observe that an NMOS device has a higher I
DSthan normally expected. What could be causing this? Would the threshold voltage be larger or smaller than normal?
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5. (10 %) Compute the gate capacitance of a PMOS transistor that is UNIT size when oxide thickness is 50 angstroms. Assume lambda is .12 microns.
6. (10 %) Compute the current flow in the PMOS transistor in problem 5 when VDS = -1 v, and VGS =.7 V. Assume the mobility of the majority carriers is 90 cm2/v.
7. (5%) What values of Vgs cause depletion in the channel of a PMOS transistor?
8. (5%) What values of Vgs cause inversion in the channel of an NMOS transistor?