A. Parker EE 477L Spring 2005

Homework Assignment #2Due 4 PM 2/10/05 *

1. (15 %) Construct a compound gate that performs the function Z= NOT([X+Y][TU + V] W ). Label the sources and drains of all transistors.

2. (5 %) What could happen if we don't tie the n-well in an integrated circuit to Vdd?

3. (10 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = 2.5 v. and Vout = 2.6 v. Both transistors are "on".

4. (5 %) What is the function of a split contact?

5. (5 %) (from the video) Which is a better technique, wet etching or dry (plasma) etching?

6. (10 %) Describe one kind of parasitic device that can cause circuit problems in CMOS. What happens as a result of this device?

7. (5 %) Design rules governing the sizes of features help us avoid which major failure?

8. (20 %) Sketch the side view, down into the silicon, of an nmos transistor in a p-well. Be sure to include the well contact, and show the poly connected to metal 1 through a contact.

9. (5 %) What major problem do we avoid when poly is fabricated before diffusion in a typical CMOS process?

10. (10 %) Show a side view (down into the substrate) of the attached figure, assuming we slice vertically, as shown in the red line. You should only show features that fall directly under that line.

11. (5 %) What is the next step in fabricating a poly layer, using Fig. 1.36 from the text as your guide, and assuming that the photoresist has been applied and exposed to UV light, and the exposed photoresist removed. Assume a positive process.

12. (5 %) How do we connect the top metal layer (metal 5) to an ohmic contact in the substrate?

* You may turn in the homework in class, regular DEN, or in the box labeled EE 477L in EEB 106. Late homework can be submitted under my door.