Homework Assignment #1

EE 477 Spring 2005 Professor Parker

Due 4:30 PM 1/27/05 in EEB 348

Remote students: If you do your assignments in color, you can email rather than fax them.

1. a) The increment computation shown in the lecture is performed using complementary NAND/NOR/INVERT circuitry (See Fig. 1). Use the same style of design (use only NAND, NOR, INVERT gates) to build a circuit that implements the Boolean equation /F= [G + H + I ] K + L. You can try to minimize the number of transistors in this design.

b) The decrement computation shown in the lecture is a compound gate (See Fig. 2). Redesign your circuit from 1a) using a compound gate. Show the compound gate transistor diagram. Use truth tables to show that the NAND/NOR implementation is identical to the compound gate. Try to take advantage of don't cares to reduce the size of the truth table. Compare the number of transistors to the original design.

3. Design a level-sensitive latch that contains either a NAND or a NOR gate in the forward path and in the feedback path where an inverter is shown in the text. Can your latch be set or reset? Show the transistor circuit diagram.

4. Design a multiplexer to select between one of three inputs using NAND, NOR AND INVERT complementary CMOS gates. Does your design use more transistors than a mux built with transmission gates?

5. A latch layout is shown in Figure 1.62 on the inside front cover of the textbook. List the layers shown. Sketch a stick diagram of this layout and from that create a transistor-level circuit for this layout.

6. Sketch a stick diagram of a 2 input mux using transmission gates. You do not need to use the cell design method shown in class for this exercise.