University of Southern California
Department of Electrical Engineering - Systems
EE 477 Laboratory #3
Module Design, IRSIM and SPICE
Laboratory #3 Due April 25, 2002 4:00 PM
This lab addresses the design of a special-purpose circuit. You can use any combination of clocks you wish, since these are inputs to the circuit and you do not have to design them. You should use the cells you designed in labs 1 and 2 to build your circuit. Do not change transistor sizes here. Do not change the circuit structure of your cells. However, you can modify the layout if you can see some ways to make the circuits smaller or faster.
The circuit you are to design performs the following function: It reads in a 1-bit value every clock cycle, checking each clock cycle for the last 4 values read in to be 0110. The output signal flag is set to 1 when 0110 is found. Every clock cycle, it performs the identical function, so if a flag is found the output flag signal goes high, and the operation stops. If a flag is not found, the circuit continues reading in new values.
Here's a pseudocode description of the circuit. ! indicates a comment
module flag_finder(1-bit_value[0],flag); !Here's the description
input 1-bit_value[0]; ! the newest bit is bit 0.
output flag;
variable past_value[3:1]; ! the 3 older values are bits 3, 2 and 1, with bit 3 being the oldest bit read in
flag = 0 !initialize the flag variable
past_value = 000 !initialize the stored value
do while flag = 0
{if 1-bit_value=0 AND past_value = 011) ! check for equal values
{
flag = 1; ! the values match
}
else
{
flag = 0; ! no match found
past_value = past_value*2 + 1-bit_value; ! save new value for next comparison
}
}
end module;
For this lab, you can use any layout strategy you choose. The goal is to minimize the area·delay (the product of area and delay). Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. Pay close attention to the specific delay you are to measure.
Note that multiply times 2 is equal to a left shift. Do not build a multiplier for this lab.
1. Design your circuit and create a MAGIC layout using the cells you have already designed. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram.
2. Simulate your layout with IRSIM to ensure that it works logically. Set up the inputs so that the first five cycles there is no match and the sixth cycle there is a match.
3. Simulate your circuit with SPICE. Set up the inputs so that the first five cycles there is no flag and the sixth cycle there is a flag. The delay you should measure with SPICE is your clock cycle.
4. Measure the area of your design in square l. Compute the area-delay product of your design. Be sure you convert microns to l in order to get credit for this part of the lab.
Lab Report Contents:
1.Title page
2.Discussion and explanation of how your design works.
3.Block diagram of your design
4.Floorplan (where each cell is on your layout)
5.IRSIM outputs for your design.
6.Layout
7.Area-delay product