1. (27%) CIRCUIT DESIGN: Use CADENCE Virtuoso schematic capture to design complementary CMOS logic gates at the transistor circuit level for the following functions:
- 3 inverters,
- transmission gate,
- 2-input NAND,
- 3-input NAND, and
- a compound gate that implements the function COMPOUT =
NOT {[PQR+STU+WXY]*N}
SIZING RULES:
Your lab technology lambda is 100 nm. Assume Vdd = 1.8v. For your schematic and layout you must make the transistor dimensions in multiples of .5 lambda. Include all transistor sizes in your report.
A. The Basic Inverter #1: The NMOS transistors in the inverter should be "unit" sized, as defined in the text and lectures, and the PMOS transistors should be sized so that the C point where both transistors are in saturation should occur when Vin at C is about 0.8v. You can be off by as much as 0.1 v. Look for the current spike to tell when this occurs. This might not result in rise time = fall time.
B. The Larger Inverter #2: Size both the transistors in this inverter 4 times as wide as in the basic inverter transistors. Remember that you can put two or more unit-sized transistors in parallel in place of widening a single transistor if it helps keep your methodology consistent.
C. The Largest Inverter #3: Size both the transistors in this inverter 4 times as wide as Inverter #2. For inverter #3, experimentally perform a rough estimate for transistor k (beta) ratio by looking at rise and fall times and taking transistor sizes into account.
D. The Transmission gates: Size the transistors the same as the inverter #1 transistors.
E. The NAND gates: For the 2-input and 3-input NAND gates, use unit size NMOS transistors and make the PMOS transistors wide enough to have rise and fall times within 3 x each other in the worst case. In other words, rise time < 3 x fall time or fall time < 3x rise time.
F. The compound gate: For the compound gate, experiment with transistor widths that give output rise and fall times within 3x each other, in the worst case. Note that the sequence of inputs that give worst-case timing might be different from the required input sequences specified below. Note also that when you have adjusted the critical path, other paths may need adjustment as well. Worst-case timing and critical paths will be discussed in class. You can manipulate the Boolean equation as desired. Include your choice of worst-case path in your discussion.
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2. (20%) CIRCUIT SIMULATION: a) Simulate your transistor circuits (Cadence circuits) using SPECTRE to determine that they function properly, and to obtain information for device sizing as described above.
SIMULATION RULES:
* Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A and B. Label your outputs INV1OUT, NAND2OUT, etc.
* Attach your inverter #1 design to the output of each gate (including the inverter) prior to circuit extraction and simulation to provide a load capacitance. The output you should plot is the input to this load inverter.
* Simulation timing: Assume .05ns rise and fall time for your inputs. Hold all input values stable for at least 1.8ns.
* Show simulations of each gate with all possible combinations of inputs.
* Change the inputs in the following manner:
a) 3-input NAND: ABC = 000, ABC = 001, ABC = 010....etc.
b) 2-input NAND: For the 2-input gates AB = 00, AB = 01, etc.
c) Compound gate: For the compound gate, simulate all combinations of W, X, Y and N from 0000 to 1111, counting up in binary 0000, 0001, 0010, etc. , while holding all other inputs to 0.
d) In another test for the compound gate, hold PQR=010 and STU to 111, and then change N from 0 to 1.
Please change the inputs in the order given so that we can grade what you are doing easily.
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PART B. Logic Gate LayoutS and Layout Simulation Experiments with Combinational Cells
1. LAYOUT: (18%) Layout the cells you designed in PART A with Cadence (each circuit layout is a "cell"). Use the TSMC technology (NCSU_TechLib_tsmc02) as instructed in lab. Put at least one ntap and ptap (ohmic contacts) in each cell. If you have multiple n-wells in a cell, each needs an ohmic contact.
Required Layout Design Methodology:
1) Design all of your cell layouts so that they can be placed next to each other either vertically or horizontally without having layers connect that should not.
2) Use a uniform methodology to design all the gates, and only use metal 1 and metal 2 for interconnect.
Your goal is to insure that it is easy to build more complex designs out of your gates, and to keep the cells small, with few layer changes for each connection.
Extend your methodology to design compound gates as well.
Keep in mind as you design the inverters that you may want to alter the design later with wider transistors, so consider how you can do that without changing your layout methodology.
At this point in the semester, try to minimize the white space to create cells that are as small as possible, but easily combined into larger circuits. One hint: you could design the cells so that the output of each cell lines up exactly with an input of every cell type. The output and input can line up horizontally or vertically.
The following is one example of such a methodology:
"Design each cell to be the same height. Power and ground will be routed horizontally later, and the input to each cell could be vertical. The output should come out horizontally on the metal 2 layer. You might want to a style similar to the cells discussed in class."
This is only an example. Instead, you might choose to design each cell to be the same width, for example. You might route the inputs to the cell horizontally, and use different layer assignments than the example.
You can put contacts for inputs and outputs somewhere inside a cell that can later be accessed when you connect cells to each other. The contacts do not need to be necessarily inside, that would depend on the methodology you choose to use.
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2. (5%) VERIFICATION: Use Cadence LVS to verify that your cell layouts are identical to the schematics. Note: When doing the LVS you do not need to have the load inverter. The load inverter is only used for simulation purposes and it is not part of your cell design.
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3. (17%) Cell Layout SPECTRE Simulations
A. Simulate the cell layouts you designed using SPECTRE (inverters, NANDs, transmission gate and compound gate) with added ntaps and ptaps.
* Your device sizes should be the same as you were instructed to attain in Lab 1a. Do not adjust rise and fall times by changing transistor sizes here. The rise and fall times will be different from the schematic.
* Attach inverter #1 cell layout as a "load" to the output of each cell prior to simulation. To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell. Read the simulation output from the cell you are testing, not the load inverter.
* Insure when you create an extracted view from the layout that you include all parasitic capacitances. (Set switches-->Extract_parasitic_caps)
* For the simulation use the same inputs in the same order as you did for the schematic simulations, including your worst-case simulations.
* Use a rise and fall time for the inputs signals of .05 ns.
* Note the rise and fall times at the outputs of each cell. You do not need to submit waveforms for the rise/fall time tests.
B. Change the temperature of the inverter #1 layout (go to ADEL-->Setup-->Temperature) in the SPECTRE simulation to 105 degrees C and resimulate. Compare your simulation results.
4. (7%) ASSEMBLY: Layout a small logic block that implements the Boolean function out = (a+b)(w+x)yz using only your inverter #1 and NAND gate cell layouts. This exercise should help you tune your cells so that they can be connected easily into logic blocks for the final project. Do not simulate or resize devices. You do not need to submit a schematic.
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6. (6%) DOCUMENT: Submit your lab writeup. The lab writeup is worth 6% of the Lab 1 grade.
Turn in final transistor-level schematics, layouts and SPECTRE simulation inputs and outputs for all cells.
Lab Report Contents (in order):
1. Title page
PART A
2. Transistor schematics of gates taken from Cadence. Submit your final schematic images without the load inverter attached to the output.
3. Discussion and explanation of how you sized transistors, and the k ratio you found, including measured rise and fall times.
4. SPECTRE input and output waveforms for each gate schematic transient simulation in the form of images showing the waveforms.
5. Images of the Vout-Vin transfer curve and results of the current computations
PART B
6. Description of your layout methodology.
7. Layouts of gates, captured as images, making sure the images are high enough resolution so the grader can see layout details and inputs/outputs are labeled. Submit your final layout images without the load inverter attached to the output.
8. Table showing cell sizes (width of the cell, height of the cell and cell area for all the cell layouts). The cell area is the width times length of the bounding box of your layout.
9. Simulation waveforms for the cells.
10. Temperature simulation results.
11. Layout of the logic block, captured as an image.
FOR THE ENTIRE LAB:
12. Conclusions about the lab, especially about sizing the transistors in the compound gate.
Your lab report should be a .pdf file. Please do not submit a .doc or .docx file. Name the report as follows: LastnameLab1.pdf
Include as separate files: Each file called si.out generated in a folder called LVS showing the results either match or mis-match for each cell layout. Be sure you rename the si.out file after each cell is verified to something like NAND2.out. Otherwise it will get overwritten.
Use the "tar function" on UNIX or the Zip function to put all the files including the report into a single file. Do not put into rar format. Students submitting multiple files will lose points. Your reports must be in pdf format and zipped with the other files.
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Instructions on how to print your waveform images in color:
To get pictures from Cadence in your report:
For schematics: Use File-->Export Image. Enter a name and save as PNG
For waveforms: Please click on them, otherwise they are very hard to see.
File -> Save Image -> Image Options -> Create exact copy of window
Then enter a name and save in PNG format.
Instructions on how to print your layout images in color:
For layouts:
In the layout editing window:
File->Print
"Submit Plot" window will pop up.
You can choose plot with "header" or "notes" or disabled both
Click on Plot Options
"Plot Options" window will pop up.
‧ Display type: display
‧ Plotter Name: (change to) Generic 300 dpi Adobe Post Script Level 2 Plotter (for color images)
‧ Send Plot Only To File : (type in file name ending with .ps)
Then use distill function to convert .ps to .pdf
Another alternative is to use File-->Export Image. Be sure the grader can see enough details.
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Some Guidance from the previous TAs:
Please be sure to use alphabetic characters to begin signal names. Cadence might have trouble with names like /A or 3A.
Cadence is case sensitive. Case sensitive means that the labels in your schematic should be consistent with the labels in your layout. For example, if in my schematic I use A for the input of the inverter then in the layout I should use A for the input of the layout inverter (If I use a instead of A it won’t work).
The label for the power supply terminal in the layout should be vdd! (do not use Vdd!), for ground use gnd! (do not use Gnd!)
************ Rise/Fall time
There is an option in the rise time window that allows you to measure all the rise times in a simulation. It is the # of occurrences. The default is “single”, you can change it. If you couldn't compute the rise time or fall time using the calculator function, you can always measure it manually. It will take some practice until you get used to managing the calculator.
************Transmission gate
It is necessary to put on the schematic a floating vdd and a floating gnd in order to compare the LVS because you have them in your layout (vdd!, gnd!).
*********** Flipping layouts:
In case you need to flip the layout cells you can do the following: select the cell--> right click-->rotate and then select the rotate option of your preference.
****** A final comment
If the layout/schematic does not match, please verify all the pins and all the connections on each node. Also, please remember to put ntap and ptap on the layout. If you couldn't find the errors, then I suggest to repeat the layout again, though 99.9% of the time the LVS error is due to a wrong connection or wrong pin labels. These cells are small enough to be able to find the error. You can use the help of the LVS output file to identify the error.
Before sending the TA emails please try all the possible options and verify all possible layout/schematic errors. Do not send schematic/layout images by email unless told to do so.
Good luck!