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Assume lambda is .1 microns. Assume Vdd is 1.8 V, Vtp0 is -.4 V. and Vtn0 is .4 V. Vtpbodyeffect is -.55 V. and Vtnbodyeffect is .55 V.
Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .5 microns.
You can use these values for transistor ks (betas): ßn (kn) (beta)= 219.4 W/L _ A(microamps)/V2 and ßp (kp)(beta)= 51.9 W/L m A/V2 .
e0 (epsilon) = 8.85 X 10 -14 F/cm, eoxide(epsilon) = 3.9, and esilicon(epsilon) = 11.7.
NA=4X1018cm-3 (substrate doping)
ND=2X1020 cm-3 (source/drain doping)
NA(sw)=8X1019 cm-3 (Sidewall (p+) doping)
ni2= 2.1X1020 cm-3 (intrinsic carrier concentration of silicon)
xj (diffusion depth) =32 nm
KT/q= .026 V (thermal voltage)
Cjbsn = 17.27 x 10-4 pF/ _m 2 and Cjbswn = 4.17 x 10-4 pF/ _m (micrometer).
Cjbsp = 18.8 x 10-4 pF/ _m 2and Cjbswp = 3.17 x 10-4 pF/ _m (micrometer).
Assume drain capacitances are the same as the source (in practice they are not).
1. (10%) Compute the worst-case rising and falling RC time constants at point 6 of the circuit below using the Elmore delay method in terms of the R’s and C’s. Assume the inputs to the NOR gate for rise time are both zero and only one of the inputs to the NOR gate is high for fall time, so that all possible capacitances can be discharged. (note that the nor gate is connected to the rest of the circuit on the left side of R1 and the voltage source is to be ignored.
2. (20%) Find an Euler path for the NMOS transistors adding transistors if necessary to create an Euler path. Show the Euler path, and where you added transistors, if necessary.
3. (10%) Assume you have the following wires to place in a layout. The numbers give starting and ending x positions of the wires. Place them using the Left Edge algorithm. For this example, two wires in the same track can start and end at the same point. So, a wire can end at 4 and another can start at 4.
3,8 5,7 1,4 2,6 5,7 3,8 1,7 4,8 1,8 6,7
4. (8%) In a large chip, clock signals can arrive 10ps early and 90ps late, the width of transistors also have 10% variation. How do the early and late clocks affect the clock cycle time (clock period)?
5. (5%) What timing parameter are we measuring from 50% input value to 50% output value?
6. (7%) Why do materials on both layers have to extend 1 lambda beyond the contact cut?
7. (10%) What design rule for metal layers helps prevent short circuits?
8. (10%) Ernie designs a positive edge triggered flip flop that can selectively load with a new D value when Load is High. Describe the tim