1a) (10%) Design a 3-input NAND and 3-input NOR transistor circuits with inputs A, B and C in a technology where mn/mp = 4, Vtn = -Vtp , all transistors are minimum length, and minimum transistor gate width = 300nm. Size the transistors to get the smallest possible designs where worst case rise time = worst case fall time.
1b) (10%) On the transistor circuit diagrams, locate all the diffusion capacitances that will be charged/discharged for both gates.
1c) (15%) Identify the input transitions leading to worst case rise and fall times for both gates (all possible capacitances are getting charged and discharged).
1d) (10%) Show the critical (slowest) paths on the NAND and NOR gate circuit diagrams.
1e) (5%) Give a case of input values for the 3-input NAND where not all capacitors are charged.
2a) (5%) Consider the compound gate drawn on the next page: What is its logic function Out = ?
2b) (10%) Locate all the drain and source capacitances of all the NMOS and PMOS transistors that will be charged/discharged.
2c) (10%) Identify the critical path for worst-case rise time. Mention the logic level of all 10 inputs. Your answer should only give the final logic levels of all inputs, transition is not required.
2d) (10%) Repeat part c) for worst case fall time.
3) (15%) List the steps required for creating a NMOS transistor, and draw a cross-section of the NMOS transistor from source to drain, labeling each layer/feature in the order fabricated.
