EE477 - HW3

Homework Assignment #3

EE 477 Spring 2018 Professor Parker

Hardcopies due in EE 477 box in EEB Basement 5 PM Feb 12, 2017

OR Ecopies due 5 PM Feb 12, 2017 using Assignment Dropbox on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

1) Consider the CMOS inverter shown. Given: V_tN = -V_tP = 0.4 V, K_N = K_P and Vdd = 1.8V and Gnd = 0.0v.

1a)(10%) Decide the regions of operation of each transistor (refer to the V_out vs V_in curve for inverter along with analysis done in class).

b) (15%) Based on your answer, write the current equations of each transistor and solve for V_out.

2) Given below is the same circuit as Homework Assignment 2 Problem 3, i.e. V_tN = 0.7V, V_tP = -0.5V. The input is now 0.0v (Gnd). Vout is initially charged to Vdd = 1.8V.

2a) (10%) What are the regions of operation of the NMOS and PMOS transistors as V_outchanges over time? Show your calculations.

2b) (5%) Is there any region of operation that is impossible for the NMOS or PMOS to be in? If yes, why?

3a) (12%) Assume an inverter with V_tN = 0.7V, V_tP = -0.5V, Vdd = 1.8V. You need an inverter where V_M = Vdd/2 (V_M is the input voltage at which both transistors are in saturation). Find the ratio K_P/K_Nthat can result in V_M = Vdd/2.

3b) (8%) If V_in = Vdd/2, what is the range of V_out for which both transistors could stay in saturation?

3c) (10%) If K_p = 51.9 W_p/L_pma/v² and K_n = 219.4 W_n/L_n ma/v², and both transistors are minimum length, what is the ratio of device widths?

4a) (5%) Define the terms V_OHmin, V_IHmin, V_ILmax and V_OLmax, and arrange them from lowest value to highest value.

4b) (10%) If we alter K_P/K_Nso thatK_P=K_N in Problem 3, what happens to the inverter voltage transfer curve? 4c) (5%) Does each noise margin increase or decrease?

Old midterm questions:

2. (5%) An inverter has V_in = 0.3v. Give the inequalities necessary to show the region of operation of the PMOS transistor and give the region. V_tn = .4 v., V_tp = -.4 v,

V_tn(body effect) =.55 v., V_tp(body effect) = -.55 v.

6. (5 %) Assume the PMOS transistors in a 6-input NAND gate are unit size (w_p = 4 lambda = 400 microns). All transistors have minimum channel length. Approximately how wide should the NMOS transistors be to have equal rise and fall times?