b) 3 pts Are there any unnecessary transistors that could be removed? Circle them.
2) 10 pts Use transmission gates to design a 3-input multiplexer with inputs A,B,C.
3) You are given the function: X = A+(B.(C+D))+(E.F)+(G.H)
a) 5 pts Draw its logic gate diagram using positive gates (AND, OR) only.
b) 10 pts Redraw its logic gate diagram replacing all the positive gates with negative gates (NAND, NOR, INV). Do not manipulate the logic equation – replace the gates as shown in class.
c) 15 pts. Draw the stick diagram of each unique negative gate you have used in part b (i.e. if you have used 2 gates of the same type and number of inputs, just draw the stick diagram once).
d) 10 pts. Draw a compound gate transistor level diagram of ~X.
4a) 10 pts. Show the truth table for a full adder and write the logic equations for Sum (S) and Carry-out (Cout).
4b) 10 pts. Show a logic design for the adder Sum and Carry-out using And, Or, INV and XOR gates.
4c) 10 pts. Show a compound gate at the transistor level for the Sum circuit. You may need an inverter at the output.
5) 5 pts Assume the delay of a circuit block is given as 0.69RC, where R and C are equivalent resistance and capacitance of the block (More on this equation later in the semester). You have a circuit made up of 3 blocks connected in series with equivalent R and C given below:
R1 = 1.2MΩ, C1 = 3.4pF; R2 = 1.5Ω, C2 = 7nF; R3 = 7kΩ, C3 = 8.3fF
Find the total delay of the circuit by adding delays of the 3 individual blocks. This is just a computation problem to review how calculations are performed.
Hint: For a list of powers of 10, see http://www.physlink.com/Reference/DecimalPrefixes.cfm .
6) 5 pts Ernie Engineer uses an NMOS pass transistor as a switch to transfer 1’s and 0’s when the switch is closed. Will the switch work perfectly to transfer 1’s and 0’s?
