EE477 - f15 hw6

Homework Assignment #6

E477 Fall 2015 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 11/16/15

OR Ecopies due 5 PM 11/16/15 using the "Assignment" Function on DEN

Assume lambda is .1 microns. Assume Vdd is 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V. Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .5 microns. You can use these values for transistor betas: βn (beta)= 219.4 W/L μ A(microamps)/V² and βp (beta)= 51 W/L μ A/V² .

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9*ε₀.

ε_silicon(epsilon) = 11.7*ε₀

N_A=4X10¹⁸cm^-3 (substrate doping)

N_D=2X10²⁰ cm^-3 (source/drain doping)

N_A(sw)=8X10¹⁹ cm^-3 (Sidewall (p+) doping)

n_i²= 2.1X10²⁰ cm^-3 (intrinsic carrier concentration of silicon)

x_j (diffusion depth) =32 nm

KT/q= .026 V (thermal voltage)

1) (15%) In the figure below, we show two possible designs for the same Out function. Analyze the cases and compare them using Elmore RC delay. There is no wire capacitance or resistance. In both cases, all transistors are unit sized.

2)a) (10%) In the figure below, assume for each individual gate (compound gate, NAND, and inverters) that rise time is equal fall time, where Rp=500 ohms. For each individual gate (compound gate, NAND, and inverters): Cgp=Cdp, Cgn=Cdn; Cgn=20 ff. Rp and Rn are the channel resistance for a single nMOS and pMOS transistor. Assume the pi-model for the wire (we only model the wire for the specified section in the figure). The wire resistance and capacitance are Rw= 100 ohms and Cw =400ff. For the transmission gate assume the PMOS size is the same as the PMOS of a single inverter and the NMOS size is the same as the NMOS of a single inverter. Compute the rising RC time constant at the input of the NAND. Use Elmore RC delay analysis.

2b) (10%) Insert a pair of inverters 1/3 and 2/3 of the way along the wire. For the inverters, assume rise time equal to fall time, so that Rn=Rp = 500 ohms, Cgp=4*Ggn; Cdp=Cgp, Cgn=Cdn, Cgn=20 ff. Use pi-model for the wire. The wire resistance and capacitance are Rw= 100 ohms and Cw =400ff. Compute the rise time at the input of the NAND using Elmore RC delay analysis. Compare this result with the one found in part (a) using the same method (Elmore RC delay analysis).

3) (10%) Assume Keq and Keq(sw) to be equal to 1 for the drain-substrate junction capacitance Cdb computation. Compute the diffusion capacitance of a diffusion with dimensions of 12um width and and total diffusion length of 8um for a PMOS transistor.

4) (10%) Compute the gate-source side of the channel junction capacitance for an NMOS transistor in linear and saturation region. The NMOS transistor dimensions are: W=10 lambda, L= 2 lambda. Assume L_D=10 nm.

5) (5%) Use the fringing field figure on p. 274 of the text. Assume w/l = 0.6, and w/h = .5. Estimate the fringing field factor if t/h = 1. In terms of the parameters in the figure, describe a possible way to minimize the fringing field factor.

6) (10%) A control signal driven by inverter A with unit size transistors fans out to drive 10,000 other identical 2-input NAND gates (only one input of each NAND is connected to the wire). Assuming wire resistance and capacitance are negligible, design a superbuffer to drive this control signal. You can assume Cdn=Cdp=Cgn=Cgp=C for all NAND gates. Indicate the number of stages (without including the first unit size inverter A) and the device sizing for each stage.

7) (10%) Ernie designs a positive edge triggered flip flop that can selectively load with a new D value when Load is High. Describe the timing problem that exists if Ernie lowers load late, after clock has fallen.

8) (10%) Describe in your own words the material discussed in lecture notes 20-3-15, 20-4-15, and 20-5-15.