EE477 - f15 hw5

Homework Assignment #5

Hardcopies due in the course boxes on the third floor of EEB 5 PM 11/6/15

Ecopies due 5 PM 11/6/15 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

Assume for the problems below that

V_dd= 1.8 V, V_tp = - 0.4 V, V_tn = 0.4 V, V_tp,BE = - 0.5 V, and V_tn,BE = 0.5 V.

T_ox= 41 angstroms for thinox, and 5000 angstroms for thick oxide.

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9.

lambda = 0.1 micron.

C_jbsn = 9.725 x 10^-4 pF/ μm² and C_jbswn = 2.27 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

C_jbsp = 11.57 x 10^-4pF/ μm² and C_jbswp = 1.8 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

x_j (diffusion depth) = 0.1 microns.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

^{1. (10%) Size a 3-input NAND gate to have the rise time faster than the fall time by a factor of two in the worst case.}

^{2. (15%) Use the compound gate shown below. Label all drains and sources. Show an identical Euler path for both NMOS and PMOS transistors by listing transistor inputs on both paths. If you cannot find a complete Euler path, you might need to add an extra transistor or two. Do not rearrange the transistors.}

^{3. (20%) Give a stick diagram for the compound gate in Problem 2 above, using the Euler path you found.}

^{4a. (10%) Find the expression for Wp in terms of Wn for the transistors in the longest path in the compound gate above to give equal rise and fall times in the worst case. Note: in case you added extra transistors, then you need to use the compound gate with the extra transistors.}

^{4b. (10%) Size the transistors in the OFF critical paths so that the resistance on each path is equal to the resistance of the critical path. Express your solution in terms of Wn for the nmos transistors and in terms of Wp for the pmos transistors. Assume transistors in the critical path are labeled as Wp for pmos and Wn for nmos.}

^{5. (10%)}How many diffusion capacitances get charged/discharged in the worst case in the compound gate above that affect the output node? Note: Assume just for this problem no diffusion regions are shared and that the diffusion capacitances for pmos and nmos transistors are the same regardless of the size of the transistors, so you have Cdn and Cdp.

^{6. (15%) A design has a number of common inputs/outputs that need to be connected. Use the left edge algorithm to connect common inputs using as few tracks as possible. The starting and ending positions of each common input are given below. You can assume the inputs come from either the top or the bottom of the channel to make the problem easier. If two wires start or end at the same point that does NOT mean they are or should be connected.}

^{A (1,4)}

^{B (3,9)}

^{C (3,8)}

^{D (1,5)}

^{E (7,9)}

^{F (6,14)}

G (13,14)

H (11,14)

7. (10%) Assume we have a positive edge-triggered flip flop designed with transmission gates and inverters.

a) Draw the flip flop gate level diagram and highlight the pathway on the flip flop that corresponds to the setup time.

b) Can the hold time be changed by changing the flip flop design?

c) Provide us with the expression for the smallest clock cycle that ensures proper functionality of the flip flop.