EE477 - f15 hw3

Homework Assignment #3

EE 477 Fall 2015 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 9/25/15

OR Ecopies due 5 PM 9/25/15 using the "Assignment" Function on DEN
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

Assume for the problems below that V_dd = 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

lambda = 100nm

1. (10%) A PMOS transistor has Vs = 1.3 V , V_d = .9 V. V_g = .2 V. What region of operation is it in?

2. (10 %) An NMOS transistor has Vs = .2 V. V_d = 1.3 V. Is the transistor in the saturation region of operation when Vgs =1.3 V?

3. (5%) Show a cross section and identify the parasitic transistors that cause latch up. How does a twin-well technology prevent latchup?

4. (5%) Assume the channel between drain and source of an NMOS transistor is formed so that the transistor is in linear region. If we continuously decrease slowly Vgs voltage while keeping Vds constant, what would happen to the electrons underneath the gate area? Would the transistor be at t=infinity in linear, saturation, or cut off region?

5. (7%) Give us 2 design rules that prevent short circuits and 2 design rules that prevent open circuits.

6. (10%) Identify on the graph the portion(s) affected by the term Vds/2. Why do we typically ignore this term? When can't this term be ignored?

You will probably want to wait until after Tuesday's lecture to work the remainder of these problems 7-10 below.

7. a) (5 %) A PMOS transistor is used as a pass transistor (switch). The input voltage is Vin = 0 V. The gate voltage Vg=.2 V. The voltage Vout = 1.4 V at time t = 0+. What is the final output voltage at t = infinity?

b) (3%) Does the PMOS transistor have body effect when t approaches infinity?

c) (10%) Assume the transistor width is three times minimum size and the length is twice minimum size. Compute the drain current flow I_DS^{at t = 0+ and at t=infinity.}

8. a) (7 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = 1.1 V and Vout = .3 V. Vgn = 1.4 V, and Vgp = 0 V.

b) (8 %) What regions are the two transistors in when t approaches infinity? Be sure to justify your answers.

9. a) (10%) In the circuit below, what are the voltages at node A and Out at t=infinity?

b) (5%) If the input Vin cannot be transferred to the output, what would be the range of voltages that you could apply to the gate of the nmos and/or pmos transistors to transfer Vin. Assume you can use a negative power supply.

10. (5%) What is the effective channel resistance of a PMOS transistor of 1.2 microns width and minimum length? Assume Vgs=-1.7 V, Vds= -.5V, Vg=0.