Homework Assignment #2

EE 477 Fall 2015 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 9/18/15

OR Ecopies due 5 PM 9/18/15 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

1a. (10%) Design a positive edge-triggered flip flop that updates its output when clock rises and has a synchronous Reset signal. When reset is asserted and clock is high the output is set to 0. The flip flop should contain two latches, as described in class. The flip flop should load new data when reset signal is not asserted. New data is only stored if Reset is not asserted. Show the gate-level diagram. You do not need to draw what is inside of each gate. Show us an implementation using transmission gates for the multiplexers and clearly label the inputs to each transistor.

1b. (10%) Design a negative edge-triggered flip flop that updates its output when clock falls and has an asynchronous Reset signal. When reset is asserted the output is set to 0 regardless of the clock. The flip flop should contain two latches, as described in class. The flip flop should load new data when reset signal is not asserted. New data is only stored if Reset is not asserted. Show the gate-level diagram. You do not need to draw what is inside of each gate. Show us an implementation using NAND gates and/or INVerters for the multiplexers and clearly label the inputs.

1c. (5%) In the implementation for problem 1b, If a student decides to implement the reset function by only replacing the inverter in the feedforward path at the output of the flip flop with a NAND gate (assume that Reset_bar is available), would this design work? Provide us with a concise and clear explanation of no longer than two or three sentences.

2. (5%) In the logic circuit given in lecture notes 5-3-15, we switch the gate inputs at each transmission gate in the bottom path, so that /A --> A, /B --> B. Explain in a clear and concise manner (no more than three sentences) how would the output be affected if A=1, B=1?.

3. (10%) Use transmission gates to build a 3 input XOR function. The inputs A, B, C and their complements are available.

4. (5%) Sketch the steps involved in patterning metal2 using a positive photoresistance.

5. (5%) List the photolitography steps involved in the connection between an n+ diffusion and metal 1. Assume n+ diffusion needs to be deposited.

6. (5%) What are the two materials involved in the formation of the gate region?

7. (5%) Give one reason to use thick oxide instead of thin oxide outside of the gate region.

8. (10%) Review lecture notes 4-6-F15 and 4-7-F15 and discuss in your own words the material covered by Prof. Parker, without using diagrams. Be sure to explain the materials used to make a transistor, and the changes under the gate as the gate voltage is applied.

9. (10%) Sketch the cross section of an NMOS and a PMOS transistor and clearly label the materials and assign a number to each layer that shows the order they are deposited.

10. (10%) In the figure below, draw the cross-section down into silicon along the horizontal yellow line. Contact us if you are having trouble determining layers. Green is n-well, blue is metal 1, magenta is metal 2, cyan (the lightest color) is metal 3.