EE477 - f15 hw1

Homework Assignment #1

EE 477 Fall 2015 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 9/11/15

OR Ecopies due 5 PM 9/11/15 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

1a. (15%) Give the Boolean expressions for the outputs of a combinational circuit multiplier. The multiplicand is a3a2a1a0, and the multiplier is b3b2b1b0 (a3 and b3 are the most significant bits). The outputs are P7P6P5P4P3P2P1P0 (P7 is the most significant bit). Use these labels for the Boolean expressions.

1b. (15%) Show a circuit diagram at the gate level of the multiplier in Problem 1a above. You are free to use any combination of NAND, inverter and/or NOR gates. There is no need to minimize the number of gates in your implementation.

2a.(10%) Show the gate level using any combination of complementary NAND, inverter and/or NOR gates for the following function:

Out = /[(A+B)CD +/E+(F+GH)I + JK(L+MNO)]

Inputs include A, B, C, D, E, /E, F, G, H, I, J, K, L, M, N, and O.

2b. (10%) Show the stick diagrams of each unique gate type you used in Problem 2a, labeling the layers or using colors for the different layers as shown in lecture. If you have 3 2-input NAND gates, you only need to show one of them.

3a. (10%) Show a compound gate transistor-level circuit diagram of the function given in Problem 2a. Do not manipulate the function.

3b. (3%) If you were to show the compound gate implementation of the complement of this function without adding any extra inverter at the output, explain in no more than two or three sentences how you would do it. You do not need to show the implementation.

5. (2%) Compare the implementations in Problem 2a and Problem 3a in terms of the number of transistors.

6. (5%) Show a stick diagram of a 5-input NOR gate, labeling the layers or using colors for the different layers as shown in lecture.

7. (5%). Review and explain in your own words the timing issue with control inputs Pickx and /Pickx in the transmission gate example discussed in the lecture.

8a. (5%) Sketch the output signal Out for the given timing diagram below. Assume ideally that the output keeps its value even if the control signal is disabled.

8b. (5%) Briefly discuss in a concise manner (no more than three sentences) what would happen to the output during the transition when the Control signal changes from high to low if the transmission gate output is connected to a huge capacitance.

9. (15%) Design a latch at the gate/transistor level that selects between inputs D0, D1 and D2 plus the feedback path Q. The latch should load when clock is high. The latch can be synchronously reset when clock is high. The reset signal when applied should send the output of the latch to 0 regardless of the value of the select signals. Reset means the output of the latch that is fed back to the mux, Q, is low. D0 should be transferred when select1 is low and clock is high. D1 should be transferred when select1 is high, select2 is low, and clock is high. D2 should be transferred when select1 is high, select2 is high, and clock is high. The multiplexers used should be constructed using transmission gates. Please clearly mark the inputs (D₀, D1 and D2), controls (select1, select1_bar, select2, select2_bar and reset), clock, clock_bar, and outputs (Q and Q_bar) on the circuit diagram.