Review Comments for Midterm 2: Lectures 10-16

Lecture 10: This was on the first midterm but it is fundamental so you should review it anyway.

Lecture 11: The first couple of pages were on midterm 1, but you should review anyway. The second midterm contents start on p. 4.

Basic Concept: You should be able to draw equivalent circuits

Basic Concept: P. 5, all capacitances get charged and discharged in the worst case. A common misconception is to only include PMOS capacitances in rise time, and NMOS in fall time.

Basic Concept: p. 5 Change channel resistance by changing transistor channel widths, not channel lengths

Basic Concept: p. 6 Channel resistances depend on transistor mobilities. A common misconception is to assume always that PMOS devices are 4x wider, or 2x wider than NMOS in the inverter.

Method: p. 6 Use the ratio method as shown in the inverter example (also NAND p. 7 and NOR p. 8) to size devices, depending on rise time - fall time relationship desired.

Basic Concept: Setting rise time = fall time helps balance high and low noise margins. A common misconception is to assume we always want rise time = fall time.

Basic Concept: The RC time constant gives you relative time information, not absolute time information. It is used to understand circuit performance and to compare designs.

Lecture 12: Reviewed for Midterm 1

Lecture 13:

Basic Concept: p. 1 make sure when testing worst case fall time all capacitors get charged before testing fall time. When testing worse case rise time, make sure all capacitors get discharged before testing rise time.

Basic Concept: p. 1 Capacitances tied to Vdd or Gnd on both sides are not included in RC time constant computations.

Basic Concept: p. 3 For compound gates, you may not be able to charge/discharge all capacitances through the most resistive path. You should compute RC

and R

C and see which is greater.

Basic Concept: p. 4 Identical Euler paths in the PMOS and NMOS parts of a compound gate make layout easy by specifying the order of inputs in the layout. Common misconception is that you need to have both NMOS and PMOS paths identical to have an Euler path. An Euler path is a mathematical construct. Idential PMOS and NMOS Euler paths make layout easier.

Lecture 15: (there is no lecture 14):

Method: p. 7 gives ideas on layout when no Euler path can be found.

Lecture 16: p. 2-3 Common misconception that reducing the number of literals in a Boolean expression always yields a smaller layout. If an Euler path can't be found, the layout could be larger than one with more literals in the Boolean expression. Optimizing at the gate level might not yield the smallest lor the fastest ayout.

Method: p. 4-5 Left edge algorithm helps you decide how to make connections between different cells or even within a large cell like the compound gate.

Method: p. 5-6 Assignment of connections to metal layers can be done in several ways listed in the notes.

Method: p. 6 Layout strategy with different size transistors in the same gate.

Method: p. 7 Transmission gate layout strategies.

General method for layout: Group PMOS transistors together in a common well to minimize layout size and possibly minimize delays as well.