EE477 - f14 hw6

Homework Assignment #6

E477 Fall 2014 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 11/18/14

OR Ecopies due 5 PM 11/18/14 using the "Assignment" Function on DEN

Assume lambda is .1 microns. Assume Vdd is 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V. Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .5 microns. You can use these values for transistor betas: βn (beta)= 219.4 W/L μ A(microamps)/V² and βp (beta)= 51 W/L μ A/V² .

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9*ε₀.

ε_silicon(epsilon) = 11.7*ε₀

N_A=4X10¹⁸cm^-3 (substrate doping)

N_D=2X10²⁰ cm^-3 (source/drain doping)

N_A(sw)=8X10¹⁹ cm^-3 (Sidewall (p+) doping)

n_i²= 2.1X10²⁰ cm^-3 (intrinsic carrier concentration of silicon)

x_j (diffusion depth) =32 nm

KT/q= .026 V (thermal voltage)

1) (15%) A 4-input NAND gate has output connected to an inverter. Below there are two possible designs for the 4-input NAND gate. There is no wire capacitance or resistance. In order to speed the design up, the NAND gate is replaced by another circuit. A critical path from the new circuit is shown below. In both circuits all transistors are unit sized. Use Elmore RC delay analysis to determine which design is faster.

2)a) (15%) Connect an output of a 2-input NOR through a long wire to the three inputs of a 3-input NAND. Assume for each individual gate (NOR and NAND) that rise time is half of the fall time, where Rp=500 ohms. For each individual gate (NOR and NAND): Cgp=Cdp, Cgn=Cdn; Cgn=20 ff. Rp and Rn are the channel resistance for a single nMOS and pMOS transistor. Assume the pi-model for the wire. The wire resistance and capacitance are Rw= 100 ohms and Cw =400ff. Compute the rising RC time constant at the input to the NAND using lumped RC delay analysis. Recompute the rising time constant using the Elmore RC delay analysis.

b) (10%) Insert an inverter at 1/3 and 2/3 of the way along the wire. For the inverters, assume rise time equal to fall time, so that Rn=Rp = 500 ohms, Cgp=4*Ggn; Cdp=Cgp, Cgn=Cdn, Cgn=20 ff. Assume the pi-model for the wire. The wire resistance and capacitance are Rw= 100 ohms and Cw =400ff. Compute the rise time at the input of the NAND using Elmore RC delay analysis. Compare this result with the one found in part (a) using the same method (Elmore RC delay analysis).

3) (10%) Assume a wire is 150 microns long and the width of the wire is 10 micron. Assume Rint = .1 ohms/square, and C = 50 ff/microns. Compute the actual wire delay using the distributed model.

4) (15%) For m=1/2, compute the drain-substrate junction capacitance Cdb when the drain node voltage changes from .1 V to 1.0 V for a diffusion with dimensions of 10um width and and total diffusion length of 6um.

5) (10%) Compute the gate-source side of the channel capacitance for an PMOS transistor in linear and saturation region. The PMOS transistor dimensions are: W=12 lambda, L= 2 lambda. Assume L_D=10 nm.

6) (5%) Use the fringing field figure on p. 274 of the text. Assume w/l = 0.6, and w/h = .5. Estimate the fringing field factor if t/h = .4.

7) (10%) A control signal driven by inverter A with unit size transistors fans out to drive 10,000 other identical inverters. Assuming wire resistance and capacitance are negligible, design a superbuffer to drive this control signal. You can assume Cdn=Cdp=Cgn=Cgp=C for all inverters. Indicate the number of stages (without including the first unit size inverter A) and the device sizing for each stage.

8) (10%) Ernie connects the output of a positive edge triggered flip flop to the input of a negative edge triggered flip flop. Describe one timing rule that he will need to enforce with respect to (setup time, hold time,

clock-to-Q, clock high, clock low).