EE477 - f14 hw3

Homework Assignment #3

EE 477 Fall 2014 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 2/29/14

OR Ecopies due 5 PM 2/29/14 using the "Assignment" Function on DEN
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

Assume for the problems below that V_dd = 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V. lambda=100 nm

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

1. (10%) A PMOS transistor has Vs = 1.7 V , V_d = .9 V. V_gd = -.3 V. What region of operation is it in?

2. (10 %) An NMOS transistor has Vds = 1.2 V. V_d = 1.3 V. Is the transistor in the saturation region of operation when Vgs =1.1 V?

3. a) (5 %) A PMOS transistor is used as a pass transistor (switch). The input voltage is Vin = 1.6 V. The gate voltage Vgs=-1 V. The voltage Vout = .7 V at time t = 0+. What is the final output voltage at t = infinity?

b) (3%) Does the PMOS transistor have body effect when t approaches infinity?

c) (10%) Assume the transistor width is three times unit size and the length is twice minimum size. Compute the drain current flow I_{DS at t = 0+ and at t=infinity}.

4. a) (7 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = .6 V and Vout = 1.3 V. Vgn = 1.6 V, and Vgp = .2 V.

b) (8 %) What regions are the two transistors in when t approaches infinity? Be sure to justify your answers.

5. a) (10%) In the circuit below, what are the voltages at node A and Out at t=infinity?

b) (5%) If the input Vin cannot be transfered to the output, what would be the range of voltages that you could apply to the gate of the pmos transistor to transfer Vin. Assume you can use a negative power supply.

6. (5%) What is the effective channel resistance of a PMOS transistor of 10 lambda width and minimum length? Assume Vgs=-1.7 V, Vds= -.5V, Vg=0.

7. (5%) What type of parasitic transistors causes latchup? Briefly explain how latchup can occur.

8. (5%) Assume a channel is formed between drain and source of an NMOS transistor, so that the transistor is in linear region. If we continuously increase slowly the drain voltage, what would happen to the channel eventually? Would the transistor still be in linear region?

9. (5%) Why do we need to have some space between the p+ diffusions to the edge of the n-well?

10. (7%) What is electromigration? How can it be avoided?

11. (5%) What is the minimum distance in micrometers allowed between two unconnected metal1 features to prevent design rule violations?