Homework Assignment #1
EE 477 Fall 2014 Professor Parker
Hardcopies due in the course boxes in the basement of EEB 5 PM 9/15/14
OR Ecopies due 5 PM 9/15/14 using the "Assignment" Function on DEN
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.
1. (8%) Give the Boolean expressions for the outputs of a 4-bit combinational circuit incrementer (the 4 digit binary number is incremented by 1). Label the outputs Y3Y2Y1Y0 and the inputs X3X2X1X0. If the maximum value is incremented, the output is reset to 0000.
2. (12%) Show an implementation at the system level of the circuit incrementer Problem 1 above with half adders (if you need it you can assume that Vdd and ground are available as inputs). You do not need to show the gates inside each half adder block.
3. (10%) Show the gate level using complementary NAND, NOR and INV gates for the following function:
H = /[XZ(Y+W) +/P(Q+ST)U + (N+R)(M+LOK)]
Inputs include K, L, M, N, O, P,Q, R, S, T, U, W,X, Y, and Z. Any combination of complementary NAND, NOR and INV gates is valid. You may not use XOR or XNOR gates.
4. (10%) Show the stick diagrams of each unique gate type you used in Problem 3, labeling the layers or using colors for the different layers as shown in lecture. If you have 3 2-input NAND gates, you only need to show one of them.
5. (5%) Show an implementation of the output SUM of a Full Adder at the circuit (transistor) level using NAND, NOR, and INV CMOS gates. For an example of complementary CMOS NAND gates and inverter, See Fig. 1. Any combination of complementary NAND, NOR and INV CMOS gates is valid.
6a. (10%) Show a compound gate implementation of the function
Y= /C(A XOR B)+C(A XNOR B)
at the circuit (transistor) level (do not manipulate the function once you substitute for XOR and XNOR). You may need an additional inverter at the output of a compound gate to get correct results. Assume complement inputs are available.
6b. (3%) Is this compound gate a better design in terms of the number of transistors than a design of the same function using transmission gates? Provide a brief explanation.
7. (5%) Show a stick diagram of a 6-input NOR gate, labeling the layers or using colors for the different layers as shown in lecture.
8a. (10%) Design a latch at the gate/transistor level that selects between inputs D0 and D1 plus the feedback path Q. The latch should load when clock is low. The latch can be synchronously reset when clock is low. Reset means the output of the latch that is fed back to the mux, Q, is low. D0 should be transferred when select is high and clock is low. The 3-input MUX used in the latch should be constructed using transmission gates. Please clearly mark the inputs (D0, and D1), controls (select, select_bar and reset), clock, clock_bar, and outputs (Q and Q_bar) on the circuit diagram.
8b. (12%) Using the waveform below, sketch the outputs Q and Q_bar. Assume reset is disabled, that means no reset is applied during these cycles. The clock_bar signal is the complement of clock signal. The select and select_bar are complement of each other. Print this waveform and sketch the output signals in the assigned space.
