Homework Assignment #6

Fall 2012 EE 477

Due November 19, 2012 5:00 PM Online or Hard Copy

Solutions will be posted prior to the midterm

Worth 1.35 regular homework assignments

Assume for the problems below that

V_dd= 1.8 V, V_tp = - 0.4 V, V_tn = 0.4 V, V_tp,BE = - 0.5 V, and V_tn,BE = 0.5 V.

T_ox = 41 angstroms for thinox, and 5000 angstroms for thick oxide.

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9.

lambda = 0.1 micron.

C_jbsn = 9.725 x 10^-4 pF/ μm² and C_jbswn = 2.27 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

C_jbsp = 11.57 x 10^-4 pF/ μm² and C_jbswp = 1.8 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

x_j (diffusion depth) = 0.1 microns.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V

Assume lambda is .1 microns. Metal thickness is .5 microns.

1)a) (10%) Compute the worst-case rising RC time constant at the output of the compound gate in Homework Assignment #5 of Fall 2012 using a lumped model, in terms of R_chp, C_dp and C_dn. Assume the original gate, not one you modified to contain Euler paths.

(b) (10%) Compute the worst-case rising RC time constant at the output using an Elmore delay model, in terms of the variables given above.

2)a) (15%) Connect an output of a 2-input NOR gate through two long wires to one input each of two 2-input NOR gates, each connected to the first NOR gate through a long wire. For the NORs, assume Rchn=1000 ohms and Rchp = 4000 ohms, Cgn=Ggp=Cdn=Cdp=10 ff. For the wire assume Rw= 10 ohms and Cw = 6ff. Compare the rise and fall times at the input to the second NOR using the Elmore delay model. Use T-model for the wire. A sketch of this circuit is shown here.

b) (15%) Insert a pair of inverters 1/3 and 2/3 of the way along both of the wires from the first NOR gate to the second and third gates. Compare the fall time constant at the input of the second NOR to the fall time constant at the input of the pair of inverters going to the second NOR gate. Use the Elmore delay model. Also compare to the results of part a. Again use the T model for the wires.

3) (10%) Assume a flipflop like the one you are building in lab 2. The flip flop drives a large load capacitance at the output. Will this capacitance affect the rate at which the flip flop can be clocked? If so, what could you do to improve performance? If not, explain why the load capacitance is not a factor.

4) (15%) Use a chain of inverters to drive a 2 pF load. How many stages (n) are required in the inverter chain, assuming the first stage is an inverter with unit transistors, assuming equal delay in all stages, and assuming Cg(n+p) for the first inverter in the chain = 4 ff? You can assume Cd(source or drain) = Cgn = Cgp. How much wider (a) are the transistors in each stage than the previous stage?

5) (10%). Compute the rise time at the output of an inverter with PMOS transistor width 16 lambda, and length minimum length. Assume CL = 15 ff.

6) (10%). Assume a wire is 5000 microns long. Assume R/micron = .04 ohms, and C/micron = 2 ff. Compute the wire delay the most accurate way possible.

7) (15 %) For the network of gates shown on page 18-6 of Lecture 18, compute the total longest delay through the network starting with the rise time at the output of gates 1 and 5. Assume C_d = C_g/2. Assume gate 4 drives a load capacitance of 2C_g. Assume the transistors are unit size.

8) (10 %) A wire stretches 1cm across a CMOS chip. Assuming electrons move at .00025 m/sec , if the rise/fall time on the wire is .05 ns, are we forced to consider inductance?

9) (15%) Use the fringing field figure on p. 247 of the text. Assume w/l = 0.6, and w/h = 0.5. Estimate the fringing field factor if t/h = 0.4.