Homework Assignment #1
EE 477 Fall 2012 Professor Parker
Hardcopies due in the course boxes on the third floor of EEB 5 PM 9/17/12 OR
Ecopies due 11:59 PM 9/17/12 using the "Assignment" Function on DEN
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.
1.(10%) You are building an adder. This problem focuses on a circuit that generates the final carry out when 3-bit 2’s complement numbers A (a1,a2, a3) and B(b1, b2, b3 ) are added; a1 and b1 are the least significant bits respectively. Give the Boolean expression for the final "carry out" Cout function in terms of the 2 numbers: A (a1,a2, a3) and B(b1, b2, b3 ). a3 and b3 are sign bits.
2.(15%) Show an implementation at the gate level using complementary NAND, NOR, and INV gates of a circuit that generates the final carry out when 3-bit 2’s complement numbers A (a1,a2, a3) and B(b1, b2, b3 ) are added; a1 and b1 are the least significant bits respectively. Note: You must invert inputs if you need the complements of the inputs in the circuit. You can use gates with any number of inputs.
3.(10%)
a) Include in your design additional logic to generate a bit that detects whether or not an overflow has occurred.
b) If A (a1,a2, a3) and B(b1, b2, b3 ) are negative numbers, and they are added, can there be an overflow? If so, give an example. If not, explain why not.
4.(5%) Show the CMOS circuit for the NAND, NOR and inverter gates used in your design. Identify the drain and source terminals.
5.(15%) Show a compound gate implementation for F, given that its function is
F={/(A+B)+/(C+D)/(EF+GH(I+J))}. “/” indicates complement. Note that all compound gates result in a complemented output so you will have to arrange the equation in the form
F = /{Boolean function} to implement it as a compound gate.
6.(10%) Show a design at the transistor level of a 5-input mux. Use only transmission gates.
7.(10%) Design a latch at the transistor level that has two possible data inputs (D0 and D1) plus the feedback path (Q). The latch should load when clock is low. The latch can be synchronously Set when clock is low. Set means the output of the latch that is fed back to the mux, Q, is high. The MUX used in the latch should be constructed using transmission gates. Please clearly mark the inputs (D0, and D1), controls (select, /select, set), clock and /clock, the outputs (Q and ~Q) on the circuit diagram. “/” indicates complement
8.(15%)Show the stick diagram for a 6-input NOR gate.
9. (10%) Make a directory (folder) on your UNIX account that is called HW1. Create a small file on your UNIX account that contains your full name on the first line and your student number on the second line. Use EMACS or any other unix editor to create the file. Save the file in the HW1 directory as yourlastname.txt. Change the directory to HW1. Give the results of typing the command ls -l yourlastn* , leaving off the last three letters of your last name. If your last name is two words with a space in between, use the last word.