EE477 - f10 lab3 part2

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 Part 2 (worth 13% of final grade)

Neural Network Design, Cadence and SPECTRE

Due 12/6/10 11:59 PM

There will be no extensions so plan your time accordingly!

This lab addresses the design of a special-purpose circuit. The circuit is a network of simplified digital neurons. There are two parts to the lab, the design of the digital neuron (worth 7%) and the design of the neural network (worth 13%). You have already finished the digital neuron.

2. The "sequence detection" neural network

This part of the lab addresses the design of a special-purpose circuit to detect a sequence of bits that are input on 4 different inputs, K1, K2, K3 and K5. The first block you will build below only uses input K3. The rest of the network uses all four inputs. The basic building block in the circuit is a very simplified digital neuron that you built in Lab 3 Part 1. You will build a small network with this neuron and inverter as basic building blocks in this part of Lab 3. You can use all 6 metal layers for the network.

For the complete project, you are to assemble a "neural net" using 14 of these neurons. Besides the first block that recognizes the K3 input, there are two other blocks shown below. The sequence it recognizes isK3, K3, K3, 0, K3, K3, K3, 0, K3, K5, K1, K2, K3, 0 "0" means no inputs are high. Also test the network with the sequence K3, K3, K3, K3, K3, K3, 0, K3, K5, K1, K2, K3, 0, 0. The recognition neuron is AP14. Only one key can be pressed at a time.

If you relate these inputs to keys on the piano keyboard, it recognizes the beginning of a traditional holiday tune popular in the US. K1 is middle C. You do not have to understand this part to do the lab.

Disclaimer: What you are building here are not at all similar to biological neurons, which are significantly more complex. I am sure there is a more clever network to detect this sequence, especially if you add more features to the neurons that make them more like biological neurons.

Operation of the Neural Network:

The first three neurons in the network, N1, N2 and N3 are shown below.
Neurons N1 and N2 have their inhibitory inputs I asserted (low), as do all the neurons in the entire network except N3.
The 3 inputs shown to all neurons are for inputs A, B and C.
Input D is tied low for all neurons.
Control inputs C1, C4, C3 and C2 are tied as follows: C1 = Vdd, C4 = Vdd, C2 = Vdd, C3 = 0.0v.

The timing diagram is shown below. Note that setup, hold and Clock-to-Q delays are not shown.

Design Requirements:

You can use any combination of multiple clocks you wish, but only clock is a clock input to the circuit and you will have to design circuits to generate the other clocks. /load is not an input to the circuit. You need to generate it if you need it. Your clock should have a 50% duty cycle (high and low an equal length of time).

You should use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells or the transistor sizes execpt in your inverters unless the rise/fall times do not meet the requirements of lab 1. However, you can modify the layout in minor ways if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Make sure your ohmic contacts meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course they should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact.

You can use metal layers 1-6 for the entire neural network.

You cannot remove unused inputs or unused logic.

The Neural Network Laboratory Design Goal

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.

The Laboratory Steps For the Neural Network

1. Design your circuit and create a Cadence circuit (schematic) diagram and a Cadence layout using the neuron and inverter you have already designed. You cannot design new cells for Lab 3 Part 2. You can continue to make minor adjustments to the layouts and tune transistor sizes if you like. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram for your network Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected. Route all inputs and outputs to the edges of the layout.

2. Simulate your schematic and layout with SPECTRE to ensure that your design works correctly. The outputs should appear on the proper cycles as shown in the timing diagram, although you will have clock-toQ delays. The inputs, intermediate outputs and final output to your project circuit should be named exactly as we have named them here. It is important you follow this naming convention so we can verify that your circuit works. You will not be able to simulate all possible inputs. Choose your cases wisely if you decide to simulate more cases than those required. Please simulate the timing diagram given in the lab assignment with inputs in the exact order we specify.

3. The delay you should measure with SPECTRE is the clock cycle or clock period. However, of course, your outputs should appear during the cycle shown in the timing diagram. The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock cycle. If you compute the area-delay product wrong, or you do not compute it you will lose points.

4. Upload your report to the assignments function of Blackboard, including your layout and simulation files as a TAR file just like you did in lab 2 so that we can test (simulate) your circuit to be sure it performs as specified. Be sure to include your SPECTRE input files for the project.

Testing Sequence:

1. Reset all neurons to 0.0v output. Hold Load low.

2. Raise Load high.

3. Start clocking the neurons with the inputs shown below in the timing diagram.

Lab Report Contents:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number
A description of the network you built, including a gate or transistor level circuit diagram printed from Cadence.
The neural network layout screen capture, in a high resolution so we can zoom in.
A description of the simulation experiments you ran with SPECTRE for the network.
SPECTRE netlist files generated by Cadence, which will include the technology file, the input stimulus file and the circuitry netlist.
SPECTRE outputs (waveforms) for the neural network schematic and layout.

Items 1-4 and 6 should all be in a single report. Tar this report along with the files specified in item 5, and upload to the assignments page of the blackboard.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.