EE477 - f10 lab3 part1

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 Part 1 (worth 7% of final grade)

Module Design, Cadence and SPECTRE

Due 11/19/10 11:59 PM

There will be no extensions so plan your time accordingly!

This lab addresses the design of a special-purpose circuit. The circuit is a network of simplified digital neurons. There are two parts to the lab, the design of the digital neuron (worth 7%) and the design of the neural network (worth 13%).

1. The digital neuron

There are many inputs to the neuron:

4 data inputs to the neuron, A, B, C and D, that could be different every clock cycle
a single-bit inhibitory input I,
Load control signal, that allows the output ff to be loaded with a new value,
Reset
and a clock with 50% duty cycle.

Name your signals as shown in bold above. The output should be named AP. It is important you follow this naming convention so we can verify that your circuit works.

The basic Neuron Function:

Each data input and control input has a single bit.
The inhibitory input I is a single bit.
You need to generate all inverted inputs, including /clock.
The neuron output contains a firing flip-flop you designed in Lab 2, and the output of the flip-flop AP represents the output of the neuron.
The neuron "fires," as long as I is held high, when either AB or CD is high. If ABC or ABD is high, the neuron "fires" no matter what I is. The conditions for firing (loading a "1" into the FF) are recomputed when inputs A, B, C, D, and I change. The inhibitory input I basically prevents the neuron from "firing" when it is asserted low unless either the group ABC or ABD are all high.
After the negative edge of the clock, if the neuron fires, the output of the firing flip-flop goes from low to high. The output remains high until the next falling clock, when it is lowered if the inputs do not cause a "1" to be loaded into the FF.
Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance.
Note that you might find a way to use the compound gate you designed in Lab 1.

A block diagram of the neuron is shown below.

Neuron input/output list:

A - 1 bit
B - 1 bit
C - 1 bit
D - 1 bit
I - 1 bit
Load - 1 bit
Clock - 1 bit
Reset - 1 bit
AP (output ff) - 1 bit

Rules:

You can use any combination of multiple clocks you wish, but only clock is an input to the circuit and you will have to design circuits to generate the other clocks.
/load is not an input to the circuit. You need to generate it if you need it.
You must use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells unless your cells do not meet the requirements of lab 1 (i.e. you lost points).
You must have ntaps and ptaps according to the rules.
You can tune the circuits by changing transistor sizes as needed.
You cannot remove unused logic from your cells.

The Neuron Laboratory Goal

You will produce a working schematic and layout for the neuron.

Layout Instructions for The Neuron:

1. Make sure your ohmic contacts (ntaps and ptaps) meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course they should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts, as Cadence will do for you automatically.

2. You can use metal layers 1-3 for the neuron.

3. For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product of the entire neural network. Final project designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design.

4. Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected.

The Laboratory Steps:

1. Design your neuron circuit and create a Cadence circuit (schematic) diagram using the circuits/cells you have already designed in Labs 1 and 2. You cannot design new cells for Lab 3. Include your logic/gate level diagram for your neuron.

2. Simulate your neuron schematic with SPECTRE to ensure that your design works correctly.

Use the following sequence of inputs for initial testing:

a) Set load to 0 and keep it low. All other inputs should be 0. Reset your neuron flip flop.

b) Set load to 1and keep it high. Then test your neuron by sequencing through all combinations of inputs starting with ABCD = 0000, then 0001, then 0010 until you reach 1111, while holding I high (no inhibition) and clocking the circuit. The output should be high when at least two of the inputs are high AB or CD.

c) Now set I = 0 (inhibition) and sequence through these inputs: ABCD = 0000, then 0001, then 0010 until you reach 1111. The output AP should be high when ABC is high or ABD is high.

d) Reset the neuron flip flop. Now set load to 0 (zero). Set ABCD = 1111, and I = 1. The flipflop output should remain zero.

3. Design and simulate your neuron layout with SPECTRE using the same sequence of inputs as in Step 2. You can modify the layout of your cells from Labs 1 and 2 in minor ways in Lab 3 if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Testing Strategy for Part 1

Here is a testing strategy that might be useful to you: Design the schematic first and test. Then design the layout.

Design and test at each stage. Design the output flip-flop first. Then design the logic and the output of the logic that makes the neuron fire if the logic creates a "fire" situation. Test the logic separately first. Then add the flip-flops. Then test the entire neuron

Lab Report Contents:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number.
A description of the neuron you built, including a transistor-level or gate-level circuit diagram printed from Cadence.
A floorplan of the neuron layout.
Your neuron layout and neuron layout simulation results as images. Make sure the layout and simulation images are of high enough resolution so that we can zoom in to check things.
A description of the simulation experiments you ran with SPICE for the network.
SPECTRE netlist files for both schematic and layout, generated by Cadence, which will include the technology file, the input stimulus file and the circuitry netlist.

Items 1-5 should all be in a single report. Tar this report along with the files specified in item 6, and upload to the assignments page of the blackboard.

MPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.

Preview of 2. Neural Network Overview

This part of the lab addresses the design of a special-purpose circuit. The basic building block in the circuit is a very simplified digital neuron that you built in Lab 3 Part 1. You will build a small network with this neuron and inverter as basic building blocks in this part of Lab 3. You can use all 6 metal layers for the network.

For the project, you are to assemble a "neural net" using several of these neurons. We will tell you all the inputs, conditions, and outputs when we post the second part of the lab.

You cannot remove logic or inputs from the neurons. If they are unused you have to tie inputs to Vdd or Gnd.

Design Requirements:

You can use any combination of multiple clocks you wish, but only clock is a clock input to the circuit and you will have to design circuits to generate the other clocks. /load is not an input to the circuit. You need to generate it if you need it.

You should use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells or the transistor sizes unless the rise/fall times do not meet the requirements of lab 1. However, you can modify the layout in minor ways if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Make sure your ohmic contacts meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course they should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact.

You can use metal layers 1, 2 and 3 for the neuron. You can use metal layers 1-5 for the entire neural network

The Neural Network Laboratory Design Goal

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure, which will be the clock period.

The Laboratory Steps For the Neural Network

1. Design your circuit and create a Cadence circuit (schematic) diagram and a Cadence layout using the cells you have already designed. You cannot design new cells for Lab 3. You can continue to make minor adjustments to the layouts and tune transistor sizes if you like. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram for your neuron. Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected. Route all inputs and outputs to the edges of the layout.

2. Simulate your schematic and layout with SPECTRE to ensure that your design works correctly The inputs, intermediate outputs and final output to your project circuit should be named exactly as we have named them here. It is important you follow this naming convention so we can verify that your circuit works. You will not be able to simulate all possible inputs. Choose your cases wisely if you decide to simulate more cases than those required. Please simulate the timing diagram given in the lab assignment with inputs in the exact order we specify.

3. The delay you should measure with SPECTRE is the clock cycle (clock period). The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock cycle. If you compute the area-delay product wrong, or you do not compute it you will lose points. Your duty cycle should be 50% (high period/entire clock period).

4. Upload your report to the assignments function of Blackboard, including your layout and simulation files as a TAR file just like you did in lab 2 so that we can test (simulate) your circuit to be sure it performs as specified. Be sure to include your SPECTRE input files for the project.

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