Homework Assignment #5

EE 477 Fall 2010 Professor Parker

Hardcopies due 5 PM 11/12/2010 1st Floor of EEB, west side of building

Ecopies due 11:59 PM 11/12/2010 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

Use these parameters for the calculation:

β_n = 340.4 μA/V², β_p = -70.8 μA/V²

V_dd= 1.8 V, V_tp = - 0.4 V, V_tn = 0.4 V, V_tp,BE = - 0.5 V, and V_tn,BE = 0.5 V.

T_ox = 41 angstroms for thinox, and 5000 angstroms for thick oxide.

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9.

lambda = 0.1 micron.

C_jbsn = 9.725 x 10^-4 pF/ μm² and C_jbswn = 2.27 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

C_jbsp = 11.57 x 10^-4 pF/ μm² and C_jbswp = 1.8 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

x_j (diffusion depth) = 0.1 microns.

1. (a) (5%) Size the transistors in a 4-input NAND gate so that the worst-case rise time and fall time are equal to those of an inverter constructed with minimum-size transistors. Label the inputs A, B, C and D, with the NMOS A transistor closest to ground. Note: this inverter does not have equal rise and fall times.

(b) (5%) What is the input transition that gives the worst-case rise time?

(c) (10%) Show an equivalent circuit for the worst-case rise time (charging path) of the NAND gate you designed in part (a), with all capacitances shown. Take into account the input values that yield the worst-case scenario. Assume the minimum size PMOS/NMOS transistors have effective channel resistance R_p and R_n and diffusion capacitance C_dp and C_dn. Assume no shared diffusion.

2. The compound gate that implements the sum output of a full adder is shown in the solution to Assignment 1 problem 5. Assume we do not know the arrival time of the inputs. Assume the smallest PMOS/NMOS transistors are unit-size with effective channel resistance R_p and R_n and diffusion capacitance C_dp and C_dn.

(a) (5%) Identify a critical path on the PMOS side that gives worst-case rise time, and on the NMOS side that gives worst-case fall time. Specify the input transitions that give the worst case timing.

(b) (10%) Size the transistors in this compound gate so that the worst-case rise time = worst-case fall time.

(d) (10%) How many diffusion capacitances get charged/discharged in the worst case, assuming no diffusion regions are shared?

(e) (10%) Compute the worst-case falling RC time constant at the output using a lumped model, in terms of the variables given above.

(f) (10%) Compute the worst-case falling RC time constant at the output using an Elmore delay model, in terms of the variables given above.

3. (10%) Compute the gate capacitance of an PMOS transistor that has dimensions 8 lambda X 2.5 lambda.

4. (10%) Compute the diffusion capacitance of the source of the NMOS transistor that is closest to ground in the NAND gate in Problem (1). Use the method described in the lecture and the text. Note that this method might differ from past homework solutions.

5. (15%) Ernie Engineer designed an inverter driving a long wire (6 mm) on a special kind of metal1 (3 lambda wide) to the input of another inverter. Both the inverters have identical unit-size transistors. Ernie's boss wants Ernie to insert a pair of inverters in the middle of the wire, so the long wire is divided into two wires. Do you think Ernie will improve his wire delay if he inserts this pair of inverters? Explain your answer. Use the following parameters in this problem.

• The capacitance of this special kind of metal is 10 ff per millimeter. The resistance is 0.01 ohm per square.
• Cgn=Cgp = 100 ff, Rchn = 500 ohms, Rchp = 1000 ohms, Cdn = Cdp = 40 ff for unit size transistors.