Homework Assignment #2

EE 477 Fall 2010 Professor Parker

Hardcopies due 5 PM 9/20/2010 1st Floor of EEB, west side of building

Ecopies due 11:59 PM 9/20/2010 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

1. (35%) You are to design a new type of binary counter that continuously counts down the odd numbers from 7 to 1 and then counts up the even numbers from 0 to 6. So the sequence should be 7,5,3,1,0,2,4,6 and then repeat itself. The current number will change when the clock falls. If reset is asserted, the current number will become 0 and should stay zero until the next negative clock edge, even if reset is unasserted. Reset is an asynchronous signal. Each bit of storage should be a negative edge-triggered flip flop. Each flip flop should contain two latches, as described in class. The data loaded into the flip flop will depend on the data currently in the flip flop along with data in the other flip flops.

Your counter should be designed at the gate level. Use NAND gates to build the multiplexer at the input to each latch.

Show your solution for the counter as a gate-level diagram.

2. (15%) Draw a transistor (circuit) level diagram for a compound gate that implements the following Boolean function

/F = A * (B + C) + (/B) * D + B * (C + /D)

You can assume that A,B,C,D as well as their complementary inputs are available. Label the sources and drains of all the transistors.

3. (10%) Sketch the side view (slice down into the silicon) of a stacked contact that connects poly to metal2 using colored pens or pencils.

4. (5%) List the steps needed to pattern poly using a positive photoresist process.

5. (5%) Why do we tie the p-substrate to ground in the regions around nmos transistors?

6. (15%) In the attached figure below, show the cross-section down into the silicon along the horizontal yellow line.

7. (5%) When do MOS parasitic transistors form?

8. (10 %) What major problem could occur when poly is fabricated after diffusion in a typical CMOS process?