Homework Assignment #1

EE 477 Fall 2010 Professor Parker

Hardcopies due 5 PM 9/13/2010 1st Floor of EEB, west side of building

Ecopies due 11:59 PM 9/13/2010 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

1. (7%) Give the Boolean expression for a four-bit comparator computation with output C and inputs X (X₀, X₁, X₂, X₃) and Y (Y₀, Y₁, Y₂, Y₃.) X and Y are being compared. C is high (1) when X is equal to Y, and low (0) otherwise. X₀ and Y₀ are the least significant bits respectively.

2. (8%) Show an implementation of the comparator computation in Problem 1 at the gate level using complementary NAND, NOR and INV gates. You may not use XOR or XNOR gates.

Note: You must invert inputs if you need the complements of the inputs in the circuit. You can use gates with any number of inputs.

3. (15%) Show an implementation of the four-bit comparator from Problem 2 at the circuit (transistor) level ( for an example of complementary CMOS NAND gates and inverter, see Fig. 1 for example. ) You do not need to show the transistor level for identical gates. If you use 3 2-input NAND gates, you only need to show one of them.

4. (10%) Show a compound gate implementation of the comparator at the circuit (transistor) level, similar to the compound gate shown in Fig. 2. You may need an additional inverter at the output of a compound gate and additional inverters at the inputs to get correct results. Compare the number of transistors to the original design in Problem 3.

5. (15%) Show compound gate implementations of the sum and carry out of a one-bit full adder (assume there is a carry in).

6. (15%) Show the stick diagrams of each unique gate type you used in Problems 2 and 3, labeling the layers or using colors for the different layers as shown in lecture. If you have 3 2-input NAND gates, you only need to show one of them.

7. (10%) Show a design at the transistor level of a single-bit comparator, using only transmission gates and inverters at the inputs to the circuit, if you need inverted inputs. The output should be a "1" if the bits are equal, and "0" if the bits are not equal.

Make sure if you wire-or the transmission gates together that only one output at a time can be transmitted from the inputs, and at least one output must be transmitted. Hint: You can use "1" and "0" as inputs to the circuit as well as X and Y. Hint #2: You can put transmission gates in series to create an "AND" function, and in parallel to create an "OR" function.

8. (10%) Design a latch at the gate and transistor level that has two possible data inputs (D₀ and D₁) plus the feedback path (Q). The latch should load when clock is low. The latch can be asynchronously set and synchronously reset when clock is high. Set means the output of the latch that is fed back to the mux, Q, is high, and reset means the output is low. The 3-input MUX used in the latch should be constructed using transmission gates. Please clearly mark the inputs (D₀, and D₁), controls (select, set and reset), clock and outputs (Q and ~Q) on the circuit diagram.

9. (10%) Make a directory (folder) on your UNIX account that is called HW1. Create a small file on your UNIX account that contains your full name on the first line and your student number on the second line. Use EMACS or any other unix editor to create the file. Save the file in the HW1 directory as yourlastname.txt. Change the directory to HW1. Give the results of typing the command ls -l yourlastn* , leaving off the last three letters of your last name. If your last name is two words with a space in between, use the last word.