EE477 - f09 lab3

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 (worth 20% of final grade)

Module Design, Cadence and SPICE

Due 12/7/09 11:59 PM

There will be no extensions so plan your time accordingly!

This lab addresses the design of a special-purpose circuit. The circuit is a simplified digital neuron, including an adder and 11 D flip-flops.

The digital neuron

There are many inputs to the neuron:

3 2-bit "strengths," AStr, Bstr, and Cstr, that are loaded infrequently
3 data inputs to the neuron, A, B and C, that could be different every clock cycle
a single-bit inhibitory input I,
a 4-bit threshold value Threshold, that is loaded infrequently,
Load control signal, that allows the output ff to be loaded with a new value ~~that allows A, B, and C to be loaded,~~
load strengths control signal LoadStr, that allows new strengths to be loaded,
load threshold control signal LoadThresh, that allows a new threshold to be loaded,
Reset control signal, that resets all the flipflops to 0,
and a clock.

Name your signals as shown in bold above. The output should be named AP. It is important you follow this naming convention so we can verify that your circuit works.

The basic Neuron Function:

Each data input and control input has a single bit, except the three strengths, which are two bits each, and the threshold, which is 4 bits.
The strengths are stored in flip flops internally in the neuron, as is the 4-bit threshold value.
The inhibitory input I is a single bit.
You need to generate all inverted inputs, including /clock.
The neuron output contains a firing flip-flop, and the output of the flip-flop AP represents the output of the neuron.
When each data input A, B, or C is high, the strength of that input (stored in the strength flipflops) is added to the other strengths that have high inputs to form the total strength. If the total strength exceeds a stored 4-bit value Threshold, the neuron "fires," as long as I is held high. So if the strength of A is 01 and A is high, 01 is added to the total strength. The total strength is recomputed every clock cycle, when new inputs A, B and C are loaded. The total strength is a maximum of 1001 if all three inputs are high, and all three strengths are set to 11.
The inhibitory input I is basically a veto that prevents the neuron from "firing" when it is asserted low.
After the positive edge of the clock, if the neuron fires, the output of the firing flip-flop goes from low to high. After the next rising clock, the firing flip-flop output falls.
The neuron cannot "fire" two clock cycles in a row.
Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance.
Note that the addition function the neuron contains is not exactly the same as the compound gate you designed, but you might find a way to use the compound gate.

A block diagram of the neuron is shown below.

Flip-Flop list:

Astr - 2 bits
Bstr - 2 bits
Cstr - 2 bits
Threshold - 4 bits
Firing (output ff) - 1 bit

Rules:

You can use any combination of multiple clocks you wish, but only clock is an input to the circuit and you will have to design circuits to generate the other clocks.
/load is not an input to the circuit. You need to generate it if you need it.
You can assume reset is asserted low if you like.
You must use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells unless your cells do not meet the requirements of lab 1 (i.e. you lost points).

The Laboratory Goal

You will produce a working schematic and layout for the neuron.

Layout Instructions for The Neuron:

1. Make sure your ohmic contacts meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course they should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts.

2. You can use metal layers 1-5 for the neuron.

3. For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product of the entire neural network. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.

4. Use LVS to verify your layout prior to SPICE simulation. Important note: Any pins in your layout labeled the same should be physically connected.

The Laboratory Steps:

1. Design your neuron circuit and create a Cadence circuit (schematic) diagram using the circuits/cells you have already designed in Labs 1 and 2. You cannot design new cells for Lab 3. Include your logic/gate level diagram for your neuron.

2. Simulate your neuron schematic with SPICE to ensure that your design works correctly.

Use the following sequence of inputs for initial testing: More steps will be added to this list because we will give you an efficient strategy for you to use for testing. There are too many inputs and stored values to test all combinations.

a) Reset your flip flop.

b) Load the threshold to 0101.

c) Set LoadStr to 1 and load the neural strengths to AStr, BStr and CStr = 11, 11, 11.

d) Set load to 1and keep it high. All other inputs should be 0. Clock the circuit. Then test your neuron by sequencing through all combinations of inputs starting with ABC = 000, then 001, then 010 until you reach 111, while holding I high (no inhibition). Hold each input for two clock cycles to allow the neuron time to reset and fire before the input changes. The output should be high when at least two of the inputs are high.

e)......we will add more testing here

3. Design and simulate your layout with SPICE using the same sequence of inputs as in Step 2. You can modify the layout of your cells from Labs 1 and 2 in minor ways in Lab 3 if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

4. The delay you should measure with SPICE is the clock cycle. The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock cycle.

5. Upload your report to the assignments function of Blackboard, incliding your layout and simulation files as a TAR file just like you did in lab 2 so that we can test (simulate) your circuit to be sure it performs as specified. Be sure to include your SPICE input files for the project.

Testing Strategy

Here is a testing strategy that might be useful to you: Design the schematic first and test. Then design the layout.

Design and test at each stage. Design the output flip-flop first. Then create the combinational circuit that forces the flip-flop to reset after the neuron has "fired". Then design the comparator and the output of the comparator that makes the neuron fire if the comparator (comparing the sum of strengths to the threshold) creates a "fire" situation. Test the comparator separately first. Then create the adder that adds the 3 strengths and test it. Then create the circuitry that selects strengths to add if the corresponding inputs are high. Then add the strength flip-flops. Then test the entire neuron.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.

Lab Report Contents:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number.
A description of the neuron you built, including a transistor-level or gate-level circuit diagram printed from Cadence.
An image of the layout of the neuron.
A floorplan of the neuron layout.
A description of the schematic and layout simulation experiments you ran with SPICE.
SPICE netlist files generated by Cadence, which will include the technology file, the input stimulus file and the circuitry netlist.
SPICE outputs for the neuron as shown in Cscope images.

Items 1-5 and 7 should all be in a single report. Tar this report along with the files specified in item 6, and upload to the assignments page of the blackboard.