University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #1

Logic Gate Layout and SPICE Experiments

with Combinational Cells

Due 10/23/08, 11:59 PM Via the DEN Blackboard Assignment Function

YOU MUST WORK INDEPENDENTLY ON THE LABS: THERE ARE NO PROJECT GROUPS

1. (20%) Use CADENCE Virtuoso schematic capture to design complementary CMOS logic gates at the transistor circuit level for the following functions: inverter, 2-input NAND, 3-input NAND, and a compound gate that implements the function G = NOT {[ABC+ABD+ACD+BCD][NOT E]}. Size your transistors as discussed below.

2. (20%) Simulate your transistor circuits (Cadence circuits) using SPICE to determine that they function properly. Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A and B. Label your outputs INVOUT, NAND2OUT, etc. Show simulations of each gate with all possible combinations of inputs. Change the inputs in the following manner - ABC = 000, ABC = 001, ABC = 010....for the 3-input gate. For the 2-input gates AB = 00, AB = 01, etc. For the compound gate, simulate all combinations of A, B, C, and D, starting with E=0 and ABCD = 0000. Hold E = 0 for all combinations of A, B, C and D. Then change E to 1 and simulate ABCD = 0000, 0001, 0111, and 1111. Please change the inputs in the order given so that we can grade what you are doing easily. Attach your inverter design to the output of each gate (including the inverter) prior to circuit extraction and simulation to provide a load capacitance. The output you should plot is the input to this load inverter. When you plot your results in MWAVES use a stacked format. Do not overlay the input and output waveforms on top of each other.

Simulation timing: Assume .1ns rise and fall time for your inputs. Hold all values stable for 2ns.


For the inverter only: Measure average current in your inverter and multiply by Vdd to obtain average power. Measure over the period from .1ns before the input falls to .1ns after the input becomes low. Use the .measure command in HSpice to measure current.

3. (30%) Layout your cells with Cadence. Use the TSMC03d technology as instructed in lab. Put at least one ntap and ptap (ohmic contacts) in each cell. If you have multiple n-wells in a cell, each needs an ohmic contact.

4. (10%) Use LVS to verify that your cell layouts are identical to the schematics. You will simulate the layouts with SPICE in Lab 2. {need more details here}.

5. (10%) Layout a small logic block that implements the function OUT = NOT[AB+CD] using your inverter and NAND gate cells from Part 3. This exercise should help you tune your cells so that they can be connected easily into logic blocks for the final project. Be sure that inputs/outputs with the same name are connected on the layout.

6. (10%) The lab writeup is worth 10%.

Transistor Sizes:

The NMOS transistor in the inverter should be "minimum" transistor sized, as defined in the text and lectures, paying attention to the current design rules in the lab. For the inverter, widen the PMOS transistor channel as required so that the β's of the PMOS and NMOS transistors are about equal. You can use these values for transistor betas:


βn (beta)=219.4 W/L μ A(microamps)/V2 and βp (beta)= 51 W/L μ A/V2

Remember that you can put two or more unit-sized transistors in parallel in place of widening a single transistor if it helps keep your methodology consistent. For the 2-input and 3-input NAND gates, use unit size NMOS transistors and make the PMOS transistors twice as wide for the 2-input case, and 1.5 times wider for the 3-input case. For the compound gate, experiment with transistor widths that give equal output rise and fall times, in the worst case. Note that the sequence of inputs that give worst-case timing might be different from the inputs specified above. Note also that when you have adjusted the critical path, other paths may need adjustment as well. Worst-case timing and critical paths will be discussed in class.

Design Methodology:

Use a uniform methodology to design all the gates, and only use metal1 and metal 2 for interconnect. Make sure that you minimize the use of poly (only use poly around the gate region of each transistor). Your goal is to insure that it is easy to build more complex designs out of your gates, and to keep the cells small, with few layer changes for each connection. You want to extend your methodology to design compound gates as well. Keep in mind as you design the inverter that you may want to redesign it later with wider transistors. At this point in the semester, try to minimize the white space to create cells that are as small as possible, but easily combined into larger circuits. One hint: you could design the cells so that the output of each cell lines up exactly with an input of every cell type. The output and input can line up horizontally or vertically.

The following is one example of such a methodology:

"Design each cell to be the same height. Power and ground will be routed horizontally later, and the input to each cell should be vertical. The output should come out horizontally on the metal 2 layer. Use a style similar to the cells shown in Fig. 1.10 of the text."

This is only an example. Instead, you might choose to design each cell to be the same width, for example. You might route the inputs to the cell horizontally, and use different layer assignments than the example.


Turn in final transistor-level schematics, layouts and schematic SPICE outputs for all cells. Turn in the layout for the logic block. You do not need to simulate this block.

Lab Report Contents:

  1. Title page
  2. Discussion and explanation of how you sized transistors.
  3. Description of your design methodology.
  4. Ttransistor schematics of gates.
  5. Layouts of gates, captured as images.
  6. A file called si.out generated in a folder called LVS showing the results either match or mis-match for each cell layout. Be sure you rename the si.out file after each cell is verified to something like NAND2.out. Otherwise it will get overwritten.
  7. SPICE files extracted from Cadence schematics so we can simulate your designs.
  8. SPICE outputs for each gate schematic simulation as shown in Mwaves.
  9. Table showing cell sizes for all the cell designs
  10. Layout of the logic block, captured as an image.
  11. Conclusions about the lab, especially about sizing the transistors in the compound gate.

Use the "tar function" on UNIX to put all the files into a single file. (See wikipedia for instructions on how to tar a file). Do not put into rar format. Students submitting multiple files will lose points. Your reports must be in pdf format.


Instructions on how to print your layout and MWAVES images in color:


Here is the instruction to print layout into postscript in color.


In the layout editing window:

– Design --> Plot --> Submit

"Submit Plot" window will pop up.

You can choose plot with "header" or "notes" or disabled both

Click on Plot Options

"Plot Options" window will pop up.

‧ Display type: display

‧ Plotter Name: (change to) Generic 300 dpi Adobe Post Script Level 2 Plotter (for color images)

‧ Send Plot Only To File : (type in file name ending with .ps)


Then use distill function to convert .ps to .pdf


Here is the instruction to print mwaves:


Tools --> Print -->

Print To : File (and choose PS)

Color: (choose color)

Legend Style : (either left or bottom will be ok)


And click on "Print" on the left-bottom


A window "Open" will pop up.

Choose(change to) cds/ directory (so the .ps file will be saved under cds directory)

In the "Open:" field, type filename ending with .ps

Then click "Ok"


Submit the assignment using the Assignments function on the DEN blackboard.