Homework Assignment #5

Prof. Parker Due Nov.12 5 PM in EEB. Electronic submissions due at 11:59 PM EE 477 Fall 2008

Assignment worth 1.25 regular assignments

Assume V_dd = 2.5 v. for these problems. Assume V_tp is -.7 V. Assume V_tn is .7 V. T_ox = 57 angstroms for thinox, and 5000 angstroms for thick oxide.

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9.

lambda = .120 microns.

C_jbsn = 17.27 x 10^-4 pF/ μm² and Cjbswn = 4.17 x 10^-4 pF/ μm (micrometer). C_jbsp = 18.8 x 10^-4 pF/ μm2and C_jbswp = 3.17 x 10^-4 pF/ μm (micrometer).

x_j (diffusion depth) = 0.1 microns.

1. a) (10%) Size the transistors in a 7-input NOR gate so that the worst-case rise times are twice the length of the fall times, assuming the smallest transistors are unit size.

b) (5%) Show an equivalent circuit of the NOR gate, with all capacitances shown. For the equivalent circuit, you can assume worst case rise time.

2. (10%) Size the transistors in a 5-input NAND gate so that the worst case rise and fall times are equal, assuming the smallest transistors are twice unit width and unit length. Label the inputs and explain the combination of input changes that gives worst case rise and fall times.

3. (10%) An off-chip inverter using a special kind of CMOS circuit outputs a "high" signal when the inverter output>=2 .2 v, and a "low" when the inverter output <= 0.2 v. The on-chip inverter receiving the signal sees a high at a minimum of 2 v, and a low at a maximum of 0. 3 v. If the noise signal has an amplitude swing of plus or minus .04 v., what are the noise margins?

4 a) (10%) For the compound gate circuit shown in the fall 2008 Homework 1 solution to Problem 4a, identify a critical path on the PMOS side that gives worst-case rise time, and on the NMOS side that gives worst case fall time, ignoring the output inverter. Specify the combination of previous inputs and present inputs that gives worst-case rise time.

b) (10%) Size the transistors in problem 4 on the critical path so that rise and fall times = rise and fall times of an inverter with unit size NMOS transistor and PMOS transistor 4 X width of NMOS transistor.

c) (10%) For the PMOS transistor with A as input, size that transistor so the delay in the paths containing that transistor equal the delay in the PMOS critical path.

d) (5%) How many diffusion capacitances charge/discharge in the worst case, assuming no diffusion regions are shared?

e) (5%) Compute the worst case RC lumped time constant for this compound gate, in terms of Rchn for a unit size transistor, C_dp and C_dn.

5. (15%) Compute the gate capacitance of an NMOS transistor that has width dimensions 3 times minimum size, and 2x minimum length.

6. (15%) Compute the diffusion capacitance of the drain of an NMOS transistor that has dimensions 10 lambda wide by 4 lambda long. Use the method described in the lecture and the text. Note that this method might differ from past homework solutions.

7. (10 %) An inverter has the transistors sized so that as the input falls from V_dd to G_nd., the "C" point where both transistors are in saturation occurs at V_in = 1.55v. What does that tell us about the ratio of betas of the two transistors?

8. (10%) Assume an inverter is on segment D of the input/output transfer curve. If V_in = 1.6v, what is the maximum value of V_out to remain in the D segment?